Hi,
I am trying to simulate a mixed signal circuit. I can measure the output of analog components, but cannot measure output for digital components. I have inserted a sample below. Vo_sch1 is the output of schmitt trigger whereas Vout is the output of analog circuit (which acts as an input for the schmitt trigger).
Please advise how to view both analog and digital outputs in mixed signal circuit.
Thanks,
RL
Does Cadence Allegro Design Entry HDL have a user manual in PDF format? Where can I get its user manual, quick start guide or tutorial as created by Cadence itself?
When I use help I get a message that says "The most latest and updated tutorials for Allegro Design Entry HDL 16.6 and related tools are available on the Cadence Online Support website.". Precisely where on the Cadence website do I need to go for this purpose?
I'm new to PCB editor and I need to make a footprint for an RF connector that sits into a cutout on the edge of the board (and is edge plated around the cutout, ideally). I have to place more than a dozen of these connectors and I would like a way of easily moving them if I need to. Is there a way to add a cutout to a footprint so that I only have to place one object?
I have a capture symbol .olb file,there are many part symbols in it, but couldn't open the .Olb file now ,the file size is normal,but when open it ,there is only one line showing unreadable code...,thanks
Hi,
I've a circuit to perform temperature analysis on which contains an NXP transistor PBHV9040T.
I downloaded the spice model from the NXP site h..p://www.nxp.com/documents/spice_model/PBHV9040T.prm
During temperature sweep pspice gives the following error message "simulation aborted because VJC is negative"
Then I simulated the output characteristic curves of the transistor and I obtained the same result.
This transistor gives negative VJC value above 54 Celsius. Since the SGP equations are provided on page 253 of pspcref.pdf
I calculated this parameter by hand and the result is the same as calculated by the program.
The initial value of the VJC is such a small as 0.102 which might cause the problem.
When I asked NXP for explanation they told that they use LTspice and there is no simulation problem with that.
So the question is whether the built in SGP equations are wrong whitin the PSpice or the NXP spice model is invalid?
Would someone (VAR) please check the model?
Thanks
Hello,
when i open the CIS Explorer in Design Entry, the order in the local part database is different to the visibility frame.
Is it possible to classify the list in the visibility frame? For example in Capture.ini?
thx
I have had orcad 16.6 for about a year and have ran across a strange behavior. I click on the netlist icon and it asks for the file name, I enter the .mnl file name click OK it then says it is going to save the file prior to netlisting, I click on OK It then tells me that there are errors, which I expect as their is always something wrong that it finds. This is where the strange behavior occurs, when I click on OK the prompt goes away and no session log or netlist are created, and this is where I am stuck. I have tried rebooting my computer, i have created a new project and copied and pasted the entire (one page) design into a different file name, I get the same results, Any help out there?
Has anyone seen any issues in ADW if you open a board file right from Allegro, not using ADW?
Then saving the board file into the physical directory.
Thanks,
Jerry
I have had orcad 16.6 for about a year and have ran across a strange behavior. I click on the netlist icon and it asks for the file name, I enter the .mnl file name click OK it then says it is going to save the file prior to netlisting, I click on OK It then tells me that there are errors, which I expect as their is always something wrong that it finds. This is where the strange behavior occurs, when I click on OK the prompt goes away and no session log or netlist are created, and this is where I am stuck. I have tried rebooting my computer, i have created a new project and copied and pasted the entire (one page) design into a different file name, I get the same results, Any help out there?
If I set via "standard" definition or padstack like this
Drill hole circle 0.300mm / Regular pad circle 0.700mm / Thermal Relief, AntiPad are all NULL.
Soldermask TOP and BOTTOM are also NULL. Symbol size is 1mm.
Min. track/track and track/pad consraints are set to 0.150mm
Is there some problems I can expect. Just notice on an old design, some of the vias have soldermask, but other don't. Have same padstack, but I think those that don't have solder mask was from "copy/paste" type. Any explanation on this? Is there place in the manual where this is discussed in detail?
Thanks :)
I want to analyse cmos non-linear characteristic and get gm2-Vgs and gm3-Vgs graphics in pspice. How can I do that?
Hi,
I am trying to use Bus pin capability for creating schematic symbols in OrCAD 16.6 like below picture:
and connected bus from FPGA to it in schematic like below:
However, it fails during netlist creation and I receive mass of errors like below:
#1 ERROR(ORCAP-36036): Multiple pin [25..27]'s which have different nets connected for U1: SCHEMATIC1, 01-DDS (203.20, 2.54).
Check for incorrect packaging of all devices in U1.
#2 ERROR(ORCAP-36036): Multiple pin [25..27]'s which have different nets connected for U1: SCHEMATIC1, 01-DDS (203.20, 2.54).
Check for incorrect packaging of all devices in U1.
#3 ERROR(ORCAP-36036): Multiple pin [25..27]'s which have different nets connected for U1: SCHEMATIC1, 01-DDS (203.20, 2.54).
Check for incorrect packaging of all devices in U1.
#4 ERROR(ORCAP-36036): Multiple pin [31..39]'s which have different nets connected for U1: SCHEMATIC1, 01-DDS (203.20, 2.54).
Check for incorrect packaging of all devices in U1.
#5 ERROR(ORCAP-36036): Multiple pin [31..39]'s which have different nets connected for U1: SCHEMATIC1, 01-DDS (203.20, 2.54).
Check for incorrect packaging of all devices in U1.
#6 ERROR(ORCAP-36036): Multiple pin [31..39]'s which have different nets connected for U1: SCHEMATIC1, 01-DDS (203.20, 2.54)
.
Check for incorrect packaging of all devices in U1.
#7 ERROR(ORCAP-36036): Multiple pin [31..39]'s which have different nets connected for U1: SCHEMATIC1, 01-DDS (203.20, 2.54).
Check for incorrect packaging of all devices in U1.
#8 ERROR(ORCAP-36036): Multiple pin [31..39]'s which have different nets connected for U1: SCHEMATIC1, 01-DDS (203.20, 2.54).
Check for incorrect packaging of all devices in U1.
#9 ERROR(ORCAP-36036): Multiple pin [31..39]'s which have different nets connected for U1: SCHEMATIC1, 01-DDS (203.20, 2.54).
Check for incorrect packaging of all devices in U1.
#10 ERROR(ORCAP-36036): Multiple pin [31..39]'s which have different nets connected for U1: SCHEMATIC1, 01-DDS (203.20, 2.54).
Check for incorrect packaging of all devices in U1.
#11 ERROR(ORCAP-36036): Multiple pin [31..39]'s which have different nets connected for U1: SCHEMATIC1, 01-DDS (203.20, 2.54).
Check for incorrect packaging of all devices in U1.
#12 ERROR(ORCAP-36036): Multiple pin [31..39]'s which have differe
nt nets connected for U1: SCHEMATIC1, 01-DDS (203.20, 2.54).
Check for incorrect packaging of all devices in U1.
#13 ERROR(ORCAP-36036): Multiple pin [42..44]'s which have different nets connected for U1: SCHEMATIC1, 01-DDS (203.20, 2.54).
Check for incorrect packaging of all devices in U1.
#14 ERROR(ORCAP-36036): Multiple pin [42..44]'s which have different nets connected for U1: SCHEMATIC1, 01-DDS (203.20, 2.54).
Check for incorrect packaging of all devices in U1.
#15 ERROR(ORCAP-36036): Multiple pin [42..44]'s which have different nets connected for U1: SCHEMATIC1, 01-DDS (203.20, 2.54).
Check for incorrect packaging of all devices in U1.
#16 ERROR(ORCAP-36036): Multiple pin [52..54]'s which have different nets connected for U1: SCHEMATIC1, 01-DDS (203.20, 2.54).
Check for incorrect packaging of all devices in U1.
#17 ERROR(ORCAP-36036): Multiple pin [52..54]'s which have different nets connected for U1: SCHEMATIC1, 01-DDS (203.20, 2.54).
Check for incorrect packaging of all devices in U1.
#18
ERROR(ORCAP-36036): Multiple pin [52..54]'s which have different nets connected for U1: SCHEMATIC1, 01-DDS (203.20, 2.54).
Check for incorrect packaging of all devices in U1.
#19 ERROR(ORCAP-36036): Multiple pin [49..50]'s which have different nets connected for U1: SCHEMATIC1, 01-DDS (203.20, 2.54).
Check for incorrect packaging of all devices in U1.
#20 ERROR(ORCAP-36036): Multiple pin [49..50]'s which have different nets connected for U1: SCHEMATIC1, 01-DDS (203.20, 2.54).
Check for incorrect packaging of all devices in U1.
#21 ERROR(ORCAP-36018): Aborting Netlisting... Please correct the above errors and retry.
I really appreciate any help in this regard,
Hossein
I just started to learn this software. I looked up some tutorials online. But I still confuse on the software. I downloaded the Lite version on Cadence. So I guess I have limitation on some of the feature. Do I always start with OrCAD capture drawing the schematic, then convert the schematic to PCB layout for manufacture production.
Hello all!
I am unable to adjust the X/Y Qty for the Copy function.
I'm sure you can see why I don't want to place 1500 units when I only need a few.
Any help is appreciated.
Thanks,
James Oldiges Esq.
Hello everyone,
I'm pretty new to OrCAD and PCB design so this is probably pretty simple. I have a board outline that is made of multiple line segments and curves. I want to use the 'Z-Copy Shape' Command to create a package keepin that is slightly smaller than the board outline. When I attempt this I get this error 'Not a closed polygon or CLine. Element ignored!' Which makes sense because it was made up of multiple line segments and maybe that causes a problem. I chamfered all the corners just to make sure they were connected but that didn't seem to fix it. The line segments do not have a break in them and the polygon they form is enclosed.
Is there a way to have OrCAD recognize this as an enclosed shape or some other way to accomplish this?
Thank you! If any other information would be useful please let me know.
I am using 16.3.
I just upgraded from 9.20 to 16.6 and the same bugs are still here 15 years later and a bunch of new ones have been added. Who wrote this steaming pile of ****?
1. Cursor constantly flickers between pointer and hourglass when moving across a part.
2. When moving multiple selected components you have to click right on a component. If you click within the bounding boxes but not on the component your selection is canceled. Didn't use to be this way.
3. Moving components/nets often results in nets being dragged non-orthogonally. It wasn't like this in 9.20. How hard is it to simply check if a net will end up non-orthogonal and anchor it? Feels like it was written by a bunch of summer interns.
4. Screen constantly redraws (often multiple times) even when not required. Windows that are hidden are constantly redrawing. Reeks of lazy, sloppy code (oh something changed? Screw it, redraw everything. Do it a few times to be safe.) Heck if I change my preferences it redraws every window. WTF is that?
5. Slow, slow, slow! I'm on a 3.5 GHz Core I7 with gobs of RAM and this thing runs like it's running on a Commodore 64.
6. Cursor doesn't change to selected operation (i.e. draw a net, place a no-connect, etc.) until you move the cursor slightly. This often results in the impression that the command didn't "take". For example if I press "x" the cursor doesn't change to an "x" unless I move the mouse a little which makes me think I pressed the wrong key.
7. Window Z-ordering is poorly coded. When opening a new project the project window doesn't open in front necessarily. This caused me to lose a whole day's worth of work because I thought I was closing a different project I had just opened for reference. Sloppy, sloppy, sloppy.
8. Text doesn't display properly when zoomed out fully. Some text displays fine, other text just displays as a black box. Didn't use to be this way. No apparent rhyme or reason as to why it will or won't display properly. Oh and the bug where it doesn't use the default font is still there 15 years later.
9. Dragging/moving a large number of objects is laughably slow. The screen redraws so slowly as to be almost impossible to use.
10. No new libraries?!!!! There's been an awful lot of new ICs in the last 15 years. Would it kill you to include a few?
I remember at 9.30 they moved the entire project over to India and the program became almost unusable. I reverted to 9.20 and stayed there. I needed to update because a manufacturer-provided library is not compatible with 9.20. It's almost comical that 15 years later the program hasn't improved and is now slower and more buggy. For $1800 I expected something that at least works decently.
FWIW, I'm the President/CEO and owner of a technology company. I still do design work in addition to running the company. If my company's products were this poor we would have gone out of business by now. And don't get me started on how slow this website is. Feels like it's running on an 8086 over dial-up in some remote part of Africa.
Even if any of these bugs get addressed my guess is that it will be tasked to some entry-level engineer at "Bangladesh Software Consortium" and the fixes will be of the "if(this) then do this but if this then do this instead however if this then ignore that and just redraw everything". Spaghetti-code.
I had an old revision of the board, and I replace some Ethernet connectors with new ones.
Those are fixed, because they have fixed places on the panel I have, and I don't want to loose their position and orientation.
New Ethernet jacks are slightly longer, but I reuse older symbols, so origin is the same, grids are same. When I do update netlist with new ones, they stay exactly on the places of the old ones, but they need slight correction in y direction (for example, there can be also slight correction in x). Symbols are 90deg rotated to original position when created in library.
If I Move the component and use command line
x (new x coordinates, new y coordinates) it goes in quite different place, and show element after this show me different coordinate of one I write down
x (new x coordinates, new y coordinates) yields same thing
OK, now I try now Draftting Offset move - first time I move in y direction with 0.1 connector jumps quite a lot, then offset moves are exact, but this takes a lot of time and effort.
What am I doing wrong here? Thanks in advance!
I am using default text block sizes for reference designator silkscreen.
In your experience, can all board houses all print text block 1, which is 16x25?
Hello again,
I'm running into a weird problem. I made a board outline, mounting holes, ect and saved it as a mechanical symbol. I then go to place this symbol in my design which goes fine, but afterwards I can not click on anything in the design area or place anymore symbols. Often I can't even close the placement window. The placement window also becomes very messed like it's trying to show two things at the same time and is mostly unresponsive. The rest of the functions are fine and if I'm using a tool(delete, move, ect) I can left and right click fine. I also notice that the command window just repeatably says 'Select elements to place using tree view.' It will say this 4-9 times for no reason.
To clarify, I can click the tool bars and such, just not in the design area.
If I close and reopen the same design the problem will still be there. If I'm having the problem then open a completely new design the problem is still there. Pretty much anything I do, this problem persists. This only happens with .brd files. .dra files are completely fine. I can't really test anything to see if it causes it or not because the problem won't go away.
I don't know if I'm doing something weird that is causing this but I'm hoping someone has seen this before and knows how to fix it.
Thank you!
6 layer board,
default layers - Top, Inner2, Inner3-v, Inner4, Inner5-h, Bottom (Inner2 and Inner4 was Planes(Shields), but change them to Conductor type, i.e. routing should be possible on them.
Have 3 type of via - Via03_06, Via04_08, Via05_1, added to constraint manager. Via padstack is the same as PCB layer structure.
When I put via during routing, available planes are only Top, Inner3-v, Inner5-h and Bottom. Inner2 and Inner4 does not appear as possible layers.
Is it something in layer structure that I need to change, constraint manager or via padstacks? I try few things, but no change.
Thanks!
