Hi all.
So here's a fun one. I have an SMA connector footprint (I've inherited), that includes a shape on the top layer, obstensibly for impedance control reasons. Now here is where things get interesting. I've had to change some of the padstacks to accomodate the more relaxed (read: sane) specs of a fab house. Suddenly the changed padstacks show as having a DRC error. Reverting to the unchanged file, and examining the padstacks; I see they were flagged as "element is on a dummy net", as is the shape that straddles the bunch of them.
How was this ever accomplished? I understand that this will get taken care of when I place the part on a schematic and assign pins to a net, but the why and how seems like it might be important.
I can see no mechanism in the symbol editor to do this. I've even tried the enved command, followed by enabling logic_edit_enabled as I found discussed online, but this didn't result in anything helpful in menus, nor a working "net logic" command, as I suspect this is specific to Allegro proper, not the symbol editor. The .dra files appear to be some vulgar binary format, so no clues are evident in a text editor :(
I can find all sorts of peripheral issues, but nothing in my forum searching addressed this exact issue. Can someone please shed some light on how this was done?
Thanks a bunch in advance,
-Mike