Hello,
I have a question similar to the one posed in http://www.cadence.com/Community/forums/t/20786.aspx .
In my design I will have bare silicon chips directly mounted on the pcb (flex pcb) in a rather complex 3d setup. Those chips have wirebond pads which will be naturally connected by wirebonds to the corresponding pads on the flex. What is the best way to proceed? From what I have found, I suppose I have to create a new part in the part designer with a completely self drawn footprint for each chip and to define the wirebond pads together with a wirebond layer in their padstacks? I searched through the documentation but did not find anything resembling exactly this situation. I would be grateful if someone could point me to an appropriate example.
Thank you very much.