Hi,
I am working with Allegro PCB 16.6. I see a very strange phenomena in my design. When I try create netlist in Capture and load it to *.brd file I see that it has removed some net members of a defined net class?!. :-( I don't see why and how this can happen. Can anybody please help?!
Thanks all,
Hossein![]()
I am working with Allegro PCB 16.6. I see a very strange phenomena in my design. When I try create netlist in Capture and load it to *.brd file I see that it has removed some net members of a defined net class?!. :-( I don't see why and how this can happen. Can anybody please help?!
Thanks all,
Hossein