I'm using Allegro 16.6 S042. I have a DDR4 address bus with a driver, 3 receivers and a termination resistor. I want the bus to be matched length to each receiver. To do this, first I create the constraint (relative propagation delay) and topology for a single net in SigXplorer. There are three constraints, one per receiver. I create a net class containing all the address nets. I create an ECSet with three ECSM match groups. Then I apply the ECSet to the net class. This correctly generates 3 match groups and all the pin pairs for driver.receiver1, driver.receiver2 and driver.receiver3. However, the problem is that some of the pin pairs are in the wrong group. For example, the match group for receiver1 should have all pin pairs from driver to receiver1 but some are from driver to receiver2. The correct number of nets are in the match group, like address bit 0 will have the right pin pair but address bit 1 will be the wrong pin pair.
How do I move the pin pairs around between match groups? Since they are auto-generated, they won't let me edit them.
thanks!