Quantcast
Channel: Cadence PCB Design Forum
Viewing all articles
Browse latest Browse all 5525

Properties attached to drc error RAVEL_MARKER_DESCRIPTION = Soldermask and Board Outline Minimum S pacing on Bottom Layer EXTERNAL_DRC_VALUE = 75.0

$
0
0

Hi,

I have this annoy DRC about soldermask spacing. Could anyone help? I just want to get risk of these. Thanks

LISTING: 1 element(s)< DRC ERROR >

  Class:           DRC ERROR CLASS
  Subclass:        ALL
  Origin xy:       (2320.029 12.700)
  Constraint:      Externally Determined Violation
  Constraint Set:  Soldermask and Board Outline Minimum Spacing on Bottom Layer
  Constraint Type: EXTERNAL REFERENCE

  Constraint value: 75.0
  Actual value:     71.0

  Properties attached to drc error
    RAVEL_MARKER_DESCRIPTION  = Soldermask and Board Outline Minimum S
                                pacing on Bottom Layer
    EXTERNAL_DRC_VALUE  = 75.0

  - - - - - - - - - - - - - - - - - - - -
  Element type:    SYMBOL PIN
  Class:           PIN
  location-xy:  (2256.029 12.700)
  - - - - - - - - - - - - - - - - - - - -
  Element type:    SHAPE
  Class:           BOARD GEOMETRY
  Subclass:        OUTLINE

Viewing all articles
Browse latest Browse all 5525

Trending Articles



<script src="https://jsc.adskeeper.com/r/s/rssing.com.1596347.js" async> </script>