Dear Community,
Version - SigXplorer - 16.6
My basic requirement is to analyze sata2.0 lines - 3 Gbps from Xilinx Artix 7 FPGA for which I have received IBIS-AMI Models. I am very new to this and I am confused.
1) The way I have started is that I have taken the IBIS Model and converted them to DML Model
2) Now for experimenting I have made a small topology which I am attaching here and I have assigned DML models to inverting and non-inverting buffers for outputs as well as inputs.
3) Now when I try and do Channel Analysis - It shows the following problem:-
4) Is there some problem with the IBIS Model or where is the problem?
Can someone please help me in this? I know this may be very silly mistakes on our part.
(Please visit the site to view this file)
I have attached the IBIS Model as well.
Regards.