Hello everyone!
I got stuck with two troubles in Allegro PCB.
Look at the figure. The line between SMD and Throu hole pad was made manually. DRC show an error, because the clearance between the line and the copper pour less than 20 mil. I don't know how to convince the Allegro to increase this clearance. Of course, I can do it manually by adding Voids. But I reckon if Allegro pours a copper automatically, it have to follow its rules automatically also.
The second 'bug" you can see below. Allegro made the thermal connection and broke his clearance rules. And it didn't show violation! I got the question from manufacturing company about clearances!
Is that "bug" of Allegro? Or I did something wrong?
Image may be NSFW.
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