I am using Allegro Design Entry HDL 16.6 and in order to validate schematics of electronic designs, I would like to have a Netlist report listing nets as they are listed in the Global Navigation window.
The following picture shows an unintentional swap that took place between blocks at the top level of a hierarchical design, where MPOD_TX_N<11..0> was connected to MPOD_TX_P<11..0>.
As these connections happen between blocks and not between components pins, it does not show up at any of the reports I have tried in Allegro Design Entry HDL and Allegro PCB Designer.
For instance, as pins of an FMC connector are connected to the minipod, and the FMC pins are named in function of columns and rows, the netlist reports including only pin names do not help a lot to indetifyswaps with differential pairs.
As can be seen, it could be easily detected by a script which receives as input all the connections to a given net and applying some filtering rules such as _P and _N, or SDA and SCL, and others.
