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Gloss line allows DRC?

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Good afternoon,


I have encountered a strange behavior in Allegro PCB Design 16.6 and I would like to check if this is intended or not.

After designing a board, I used the Route > Gloss Line Parameters... function to smoothen out the tracks and make the board look tidy.

However, after the operation some tracks were allowed to go through drilling holes, or at least very close to them.

The two attached images should provide an example: the track ADC_CSB<4> is not routed around the mechanical hole in the center of the image. Any attempt to slide it manually results in a bubble, as expected. However, after the glossing operation the track is allowed to get too close to the hole. Notice that if after the gloss I try again to slide the track, it is immediately brough back to a safe distance, as if Allegro "knows" that it should not be there, so my understanding is that the constraints are set correctly (I might be wrong though).

Also note that after the gloss operation I do not get any DRC warning. We only discovered the problem when the PCB manufacturing company alerted us of it.


I would appreciate is anyone could explain what is happening and, more importantly, how to avoid it in the future.

Kind regards,

Paolo


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