Hi there,
We are design SCH and PCB involving Xilinx Artix-7 FPGA. As usual, we did pin swap during layout, and then we need to verify the swapped pin assignment in Xilinx Vivado .
We do this manually in the past, Could Cadence directly export the ".xdc" or "tcl" file which can be imported by Vivado? And how? I am using V16.6 with hotfix 20. Thanks!
I googled and found this link, but its saying "You can now generate .xdc files and Vivado TCL scripts for all the Virtex 7 devices."
