Hi! I am modifying a routed schematic/board pair that I inherited, and I would like to make sure that the modified versions are electrically equivalent before sending the board for production. This is my situation:
Step 0: I had an original schematic "version1.opj" and its routed board "version1.brd". These versions are in synch and 100% routed without any errors.
Step 1: In Capture I modified the original schematic and saved as "version2.opj". I extracted the netlist files from this updated design (pstchip.dat, pstxnet.dat, pstxprt.dat).
Step 2: In PCB Editor I opened "version1.brd" and saved it as "version2.brd".
Step 4: In PCB Editor I opened "version2.brd" and updated the netlist to point to the modified board files (using File->Import->Logic/Netlist).
Step 5: In PCB Editor I modified "version2.brd" manually to match the updated schematic.
Now I would like to make a sanity layout-versus-schematic of the modified schematic and board, before submitting for production. I found in the web a hint to how to do it (see text below), but I was unable to follow it because the explanation is not clear. Can someone please show the detailed procedure on how to accomplish this?
Thanks and regards,
Jorge.
Procedure found on the web (www.edaboard.com/showthread.php
"Open your schematic in Allegro Design Entry , Create a netlist with PCB Editor and Layout ....you ll get .dat files and .mnl file. Now in PCB Editor Import the .dat files by redirecting to the folder where those are saved. Now without doing anything just save it as.brd file and then open your .brd file again in PCB Editor . This Creates your .xml file....Sorry its a long procedure , but i found it after many trial and error methods. Do the same for the layout file which u already have.
Now using design compare , load both your .xml files in it and you ll get a neat comparison of netlists."