To preface, I'm not a layout engineer, and I have little experience with layout tools. That said, I'm using the Allegro free viewer to look at a BRD file for a Xilinx eval board. I get how relative prop delay constraints work, but I'm confused as to the results I see in the report file. Can someone explain the difference between the "Total etch length" and the "actual" length shown in the (RDly) line?
Thanks.
Item 57 < NET >
Net Name: FMC_HPC0_LA10_N
Member of Diff Pair: FMC_HPC0_LA10
Member of Bus: FMC_HPC0_LA_BUS
Pin count: 2
Via count: 2
Total etch length: 9052.231129
Total manhattan length: 4784.469 MIL
Percent manhattan: 189.20%
Pin Type SigNoise Model Location
--- ---- -------------- --------
U1.W4 BI (2899.0450 -4363.4860)
J5.C15 BI (3685.0000 -8362.0000)
No connections remaining
Properties attached to net
ECL
NO_TEST
BUS_NAME = FMC_HPC0_LA_BUS
TS_ALLOWED = ANYWHERE
RATSNEST_SCHEDULE = MIN_TREE
DIFFP_PHASE_TOL = 5 mil
Electrical Constraints assigned to net FMC_HPC0_LA10_N
relative prop delay: global group MG_FMC_HPC0_LA_BUS from J5.C15 to U1.W4 delta=0.0000 MIL tol=50.0000 MIL
static diff pair phase tolerance: 5 mil
pin order type: minimum tree
Constraint information:
(RDly) J5.C15 to U1.W4 min= 9615.1448 MIL max= 9715.1448 MIL actual= 9616.0783 MIL
target= (FMC_HPC0_LA29_P) J5.G30 to U1.U9
(3685.0000,-8362.0000) pin J5.C15,BI,TOP/TOP
35.3553 MIL cline TOP
(3710.0000,-8337.0000) via TOP/BOTTOM
8989.42 MIL cline 05_SIG2
(2918.4592,-4382.9002) via TOP/BOTTOM
27.4558 MIL cline TOP
(2899.0450,-4363.4860) pin U1.W4,BI,TOP/TOP,pin+Zall=563.8472 MIL
(SPhase) J5.C15 to U1.W4 min= 9612.0697 MIL max= 9622.0697 MIL actual= 9616.0783 MIL
DPData: gap=var (--0.0001,+0.0000) tolerance= 5.0000; max uncoupled= -0.0001
(3685.0000,-8362.0000) pin J5.C15,BI,TOP/TOP
35.3553 MIL cline TOP
(3710.0000,-8337.0000) via TOP/BOTTOM
8989.42 MIL cline 05_SIG2
(2918.4592,-4382.9002) via TOP/BOTTOM
27.4558 MIL cline TOP
(2899.0450,-4363.4860) pin U1.W4,BI,TOP/TOP,pin+Zall=563.8472 MIL