Signal/Power Integrity Problem

hi everybody,

i have a problem. i am using the SPEED2000 to extract the netlist from .brd file to run SI simulation.I have checked the error and warning into PCB Board and tool showed a note that: 

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OUTPUT                                                                                                                                                                                                                 /

WARNING [Via Placement]: Via3420::GND at (117.531mm, 19.191mm) with lower node on Signal$S3 has a placement warning                     /
WARNING [Via Placement]: Via3432::GND at (89.419mm, 19.186mm) with lower node on Signal$S3 has a placement warning                       /
WARNING [Via Placement]: Via3436::GND at (82.014mm, 19.186mm) with lower node on Signal$S3 has a placement warning                       /
WARNING [Via Placement]: Via4394::GND at (12.615mm, 10.387mm) with lower node on Signal$BOTTOM has a placement warning            /

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This is called "Node Check"

I want to ask that how to fix this node check and disappear them from the board?

This problem points a bit on the simulation field. Hope everybody help please.

Thanks so much!