Hi,
I am performing "tlsim" simulations on a net in SigXplorer that I have extracted from PCB Editor. Occasionally, I fail to run the simulation because I get a serious warning about a convergence problem.
The weird thing is, I have successfully simulated the same net with the same simulation parameters before. So I feel like there is no problem with my setup, these convergence warnings seem to pop up at random.
Has anyone else experienced the same thing? Any ideas on how to work around it?
Thanks.