Good day Engineers,
Hello Sir/ Ma'am,
I'm new into cadence and I'm having difficulties to debug the problem using Allegro PCB Design Entry HDL.
Firstly, I'm using Cadence 17.2 version. I have updated schematic file but when I try to export my ( Input BOARD Files - not updated board ) into my new ( Output Board file - Updated schematic w/ New components added) I'm having errors, these are the error
------ Oversights/Warnings/Errors ------
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Start Constraint Diff3 Import
Constraint File: C:/Users/JM/Downloads/15mh/feb27/worklib/ltc/packaged/pstcmdb.dat
Allegro Baseline: C:/Users/JM/AppData/Local/Temp/#Taaaaae74660.tmp
Start time: Thu Feb 27 12:18:27 2020
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ERROR: Schematic database has probably been reverted to an earlier version than that, which was used in the latest flow.
The basecopy file generated by the last back-to-front flow not found.
ERROR: Schematic database has probably been reverted to an earlier version than that, which was used in the latest flow.
The basecopy file generated by the last back-to-front flow not found.
ERROR: Schematic supports automatically creating XNets using DML but the Layout will not automatically create any XNets. Change setting in Layout or Schematic, re-generate files, and re-run the flow.
ERROR: Can't import electrical constraint data (pstcmdb.dat)
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Finished Constraint Update Time: Thu Feb 27 12:18:27 2020
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Much Appreciate.
John