Most of our designs are RF and we require channelized metal cover for isolation. More than once we've had via shorting issues due to either overlooking it or last minute changes. I'd like to be able to setup constraints for a DXF layer that represents the cover to any copper that's hot (any net other than ground/return). Is this possible? I'm using Cadence 17.2 PCB Designer. No other add-ons
Thanks
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