I have a design implementing two ranks of DDR4 memory consisting of 10 DRAM chips total. One rank is on the top layer and the second rank is on the bottom layer directly below. The topology is fly-by and requires many of the busses to be length matched typically to 5 or 10 mils.
Some of the data lines are routed to the top and bottom DRAM chips using via-in-pad due to routing space and convenience. The via-in-pad creates an interesting issue. The PCB thickness is 78 mils. If the trace length is to be matched to the pins connected to the via-in-pad on the top and bottom of the PCB, there would be a "trace length" difference between the top and bottom DRAM pins given that the signal layers aren't perfectly centered in the middle of the PCB. Now, I don't remember enabling "Z Axis Delay" in my OrCad PCB Designer tool, but it is enabled. I found this setting under Setup -> Constraints -> Modes -> Electrical. With this setting taking into account the via distance in the trace length, it's impossible to meet the 5 or 10 mil length matching requirement if via-in-pad is implemented.
I've done some Googling and haven't found a conclusive article or reference for including via z-direction in the DDR4 routing trace length matching. I *think* this function was enabled by default. Is via z-direction distance typically included when trace matching for topologies like DDR4/fly-by? Via-in-pad seems to be pretty common for DDR4 routing from what I can tell. It's curious I haven't been able to find more info on the subject.
My toolset is OrCAD PCB Designer Professional 17.4-2019 S016.