In other PCB/SCH tools I have used it was possible to generate a netlist from both the schematic and then from the completed board so as to verify the actual board did indeed match the schematic.
Basically it is just a netlist compare utility. Kind of handy during post processing before you send a board out to be made.
Was wondering if it is possible to do this with capture/allegro and if a utility exists to do this ?
Thanks Scott