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ultra librarian plug in for orcad
Hi,I'm trying to find a way to access Ultra librarian from orcad CIS. I watched videos and they show how UL can be accessed from orcad, but they dont show from which menu i can access UL.
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How is thieving clearance calculated
When I set a specific thieving clearance most designs will add several mm more. I wanted to find out how the thieving clearance is actually calculated.
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Regarding changing pf standard Jedec types that are available in allegro PCB...
My question is how can we change a standard JEDEC Type that is available with respect to its dimensions to make a custom library.
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add bar over net alias name in capture
how to add bar over net alias name in capture something like we do for pin name.
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Schemetic library and Package library
For cadence, does integrated library exist for schematic and PCB design?Where can I download integrated library? If integrated librar does not exist, where can I download Schemetic library and Package...
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Laser Via - Buried Via
One of our layouts slipped through with a laser via on top of a buried via (fab house caught it). I don't understand why the system didn't flag it. We had BB via stagger set at 0.3837mm, and via-to-via...
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updating symbols
hellowhat would be the best way to update a symbol?i removed a few pins from the existing symbol on the current design.so "refresh symbol" gives me an error and does not work.this is how i do but if...
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DESIGN ENTRY CIS RENUMBERING?
TWO QUESTIONS HERE:I would like to renumber REFDES on schematic pages, but I want to start at specific number on each page. For example, I want all parts on page 1 to be x100 and up, I want parts on...
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Error in importing Netlist
Hi,While importing logic from cadence design entry hdl, I got an error as shown belowSchematic supports automatically creating XNets using DML but the Layout will not automatically create any XNets....
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Editing of jedec type
I have to design a pcb for a 32 pin qfn package with 5mm x 5mm dimension. But i was not able to find any jedec type regarding this. i have used QUAD50M32WG700 but it dont have center pad. I am fully...
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cadence technology forum
hello allwhen i search on google, i notice there is another cadence technology forum underhttps://communitystg.cadence.comi can not get access to it.do you know how to get access to the forum?
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Schematic Symbols: How to hide pins on 17.2 S057
It used to be simple to hide un-used pins in a package, following this guide: Connection Symbol PropertiesOptional: Setup Pack Short for connected pins.View -> PackageEdit -> Properties[x] pins...
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I'm struggling to download a simple footprint
Hello,I'm using OrCAD 16.6 and I'm struggling to download a simple footprint. I download the footprint from snapEDA. It's just an 0805 resistor. I see the .dra file and can open it in allegro. The...
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Rigid Flex Cross Section Setup
Hi I am trying to setup Cross Section Window for my rigid flex design. There are some terms which are not present there: 1. Site file : No site file found. Because of this i cannot add adhesive top to...
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radius always returns 0 despite the actual pad diameter">axlDBGetPad(viaID "TOP" "REGULAR")->radius always returns 0 despite the...
Hello, I'm trying to read the PAD radius by:axlDBGetPad(viaID "TOP" "REGULAR")->radius always returns 0 despite the actual pad diameterand I always get 0.0 despite in padstack editor, all layers pad...
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Shifting routes and placements from one board to another
I am working on a high speed design and i do have its reference design and layout with me. I have made some changes in the reference design and now i want to export it to PCB. I want to ask is there...
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Capture - Making new part editing pin names while placing new pin
Looks like Cadence has changed the Capture library symbol editor so that you can no longer right click to edit a pin name while placing consecutive new pins?Example, I place pin 1 named "B1" . Next is...
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What properties should have a test point defined in Concept HDL Design Entry...
Hi,As a electronic designer I have defined all the test points in HDL DE. The fact is that in Allegro, these test points don't not have the property "PROBE", so although they are placed and used as...
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Orcad 16.6: test point on a THT pin
Hello, I'm working with Orcad 16.6. I've to place test point for ICT.I can place test point vias, no problem. I need to test a THT connector. Is it possibile to set component pads as test...
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Orcad 16.6: problem with "Delete Unconnected Copper" command
Hello, when I lunch the command it works properly.Here an examplehttps://ibb.co/kc0FPqVIf I stretch a trace the Dynamic Shape will be update properly (around the trace), but the void of previous...
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