What are these errors after using automatic routing?
I also have some with K C and some with P P and P S. I can not find a library of where to look up what these are?
View ArticleTaking Care Of PCB Rework Properly is Much Better Than Discarding Them
In times of difficulty to obtain components, increasing need for versatility and fast advancement cycles, tidy and economical PCB rework to conserve set up or bare published motherboard are coming to...
View ArticleShape to Route Keep Out Spacing - Automatic shape update fails
The highlighted 0V-shape in the figure below fails to update itself. It rounds the corner so that the shape creeps in to the Route Keep Out area of the component.When manually updating the shape it...
View Articleorcad capture 17.2: Bus has no name and therefore defines no signals
Hello,I was doing a DRC and got "Bus has no name and therefore defines no signals". How do I fix that?I put a bus with bus entries on the bus and wires with net aliases SCL0 and SDA0. If I double...
View ArticleWarninh: Symbol not found
Before we get into this, let me point out that I am a newbie to Allegro/Orcad PCB so please forgive me if I am making a rookie mistake.I am having a torrid time trying to bring custom footprints into...
View ArticleCreating a BOM with LibreOffice Calc
Hi,Has anybody found a way to have Allegro Schematic Capture (any version) automatically open a BOM in LibreOffice Calc rather than MS Excel? You can do the normal ASCII BOM creation and then open...
View ArticleNegative Tolerance in Relative Propagation Delay
In Electrical constraints when we want nets in a group to be +-20mil w.r.t to a manually selected target 0:20 tolerance works fine, but before we could reach this conclusion, the tool also accepts...
View ArticleBLE Wristband Beacon & LoRaWAN Wearables in Covid-19 Contact Tracing Solution
The entire world is going through a crisis due to the persistent COVID-19 and we desperately need contact tracing if we are to take up effective measures against it. In this regard, MOKO offers you a...
View Articleto import Gerber file with .dat, , .gbl and .art extension into APDL
as mentioned in title, would like to know how to import those extension file into APDL. Thanks in advance
View ArticleStep model "skinning" export in 17.4?
I found a mention in the 3D notes but wondering if the feature has been released for 17.4 sp6...Anyone find it?
View ArticleAny angle routing in Allegro PCB 17.4
Does Allegro support any angle routing? I used offset routing where I could set an angle between 4-18degree. Say suppose I want to use 24degree or any other value how can I route it.I am using Allegro...
View ArticleSetting up a bussed differential pair (DDR CLK)
Can anyone tell me how to properly define a bussed differential pair so the static phase can be tuned for each individual segment?The DDR CLK pair runs from FPGA thru five DDR components. After routing...
View ArticleHow to get the visibility of COLOR - CLASS/SUBCLASS?
I want to know if the layer is visible or not after I use:color -toggle "PACKAGE KEEPOUT/TOP"How can I get it?
View ArticleUgly icons (17.4) - can they be changed?
First time to fire up 17.4 and what the heck? I can not believe or understand the need to change the icons. I've got eye-muscle memory and literally am hunting for my icons.Has anyone else found the...
View Articlenetrev.exe crashes when attempting to update BRD file (17.2)D
I have a design in Capture CIS that will netlist without issue. When I try to update the PCB, pst files get created and then a windows dialog pops up stating that "nextrev.exe has stopped working"....
View ArticlePad_Designer.exe in 17.4?
I am currently using PCB Editor 17.4 and I am trying to download a design to import into my project and the script fails and says 'pad_designer' is not a recognized command. I know I have done this in...
View ArticleConcept HDL Export physical fail
ERROR(SPCOPK-1086): Parent part not found for the alternate part of ***.please tell me the errors detail info,and how to fix it.自动判断...
View ArticleDrill Chart can not display figure of Buried Via
Please help me to fix the display error of buried via.We use some type of Buried via:TOP - Layer2: via1-2Layer2-7: via2-7Layer7-Bot: via7-8We generate the drill chart for all, but the chart of drill...
View ArticleSub Menus are too large
My system has a problem with Allegro 17.2. At first all of the text was to small to read and the icons too small to make out even with the Icon setting set to"large" I was able to resolve the issue by...
View ArticleDrill File Missing Holes Because Generates into Multiple Files
Six layer board has 5 hole sizes. Drill chart generates correctly. NC Drill file only shows largest 3 holes. ncdrill.log shows that 3 seperate drill files files were sequentially generated all with the...
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