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Import Altium Schematic into Orcad Capture
Hi everybody,I am trying to convert an altium project (both schematic and PCB) into Orcad 17.4.I am following the guide...
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Dynamic phase tolerance
This is the first time I've used the dynamic phase tolerance. I don't have the high speed option, but it does seem to be functioning although it doesn't seem consistent. Meaning I get violations on...
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Symbol Import issue in OrCAD capture CIS 17.4
Hello Everyone ,I am using OrCAD capture CIS 17.4 Eval to design a controller board . This is my first time working with OrCAD capture CIS and I am facing a symbol import issue .When I try to import a...
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difference between the 4 layer & 6 layer
Does we select the 4 layer PCB instead of 6 layer PCB?....if i did what will happen in future i mean during the PCB design time.and the layer selection is based on cost? or else any other specified...
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Mouse recommendation for Allegro use
Hello everyone,I apologize if this is not the right forum to use for this post.I was wondering if anyone can suggest a specific mouse manufacturer/brand that is best for using with Allegro. I use...
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Allegro impedance calculation
Hello,I have an issue with Allegro calculating the impedances. I have followed this tutorial: https://www.youtube.com/watch?v=XKVQPEIeRT0 but I am getting wrong values. Even if I put same values for...
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how to display the information of bbvia
Hi All,I created the bbvias on 6 layer boardbut as I know, there should displayed the layer information like below on the via pad.despite of bbvia, however, my allegro PCB wasn't displayed like...
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How to fix the via problem ?
I am a self learner trying to duplicate the reference design from scratch.Following is the reference design board file via pattern (layer-2 GND plane):Here, drill and pads of the vias are visible and...
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Orcad CIS part group export to BOM
Hi, I'm using Capture CIS V17.XX and would like to export the group allocated in part manager to the CIS BOM. I found no way to do so, as the allocation to group dose not seem to be done by property....
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Correct use of NET_SPACING_TYPE net property to drive high voltage spacing...
In hierarchical designs, I have found that engineers are able to assign a single net to different NET_SPACING_TYPE classes at different levels of the schematic hierarchy. Ultimately, the flat net can...
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OrCAD professional fanout etch tuning creating opened nets
HiI have a weird problem - I'm trying to work on timing a matched group with the relative propagation for the net group. I did a fanout on my connector and every time I edit the etch the net that I...
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Stacked Conductors or 'Invisible' via
Is it possible to have two conductor layers stack on top of each other (without a dielectric in between them) and have allegro pcb detect connection without vias?ORIs there an 'invisible' via that I...
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Orcad-Allegro-Highlighting anything really slow after upgrade to 17.4 S008
Hi, I updated to S008 today and am seeing a huge slow down in graphic speed with highlighting.For example I have 11 parallel traces, if I pass the mouse across them at slow to moderate speed they do...
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Library Explorer Import Error(DE-HDL)
Hi, I am currently learning and using DE-HDL(17.2 ISR7) using Allegro PCB Designer(Schematic License).One of our customers gave us DE-HDL Project file, and we have to revise its library and add our own...
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Mouse scroll wheel won't pan
Hey Guys,I got a new Logitech M500S mouse and the scroll won't pan when held down, it just zooms out. Anybody have a fix for this?thanks!Gary
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Allegro EDM Flow Manager: error in cpm filed
Does anyone know how to solve this issue? since my computer is upgraded automatically today then the issue's happened even though I reinstall the cadence tool.
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Assigning net to copied Via+Cline? Alternate method for custom fanout?
I'm in the process of laying out a series of DDR4 devices consisting of two ranks of five devices each. There will be a lot of repeated routing, even within the same device. Being as I want to match...
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difference between solderpaste_top vs pastemask_top
Hello,In the pad editor, I see the word "pastemask_top" for the steel sheet stencils for the solderpaste.When I open a .dra in Allegro, I see in the color dialog both pastemask_top and solderpaste_top....
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High Voltage Net Spacing
I am laying out an isolated power supply PCB. I would like to keep 3 high voltage nets on the input side of DC/DC converters spaced appropriately from the output side of the converters to prevent...
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Issue in Step file generation
I am having problem in one of the component in my PCB, this particular component always gets shifted to board origin when I generate the step file by export option. However the 3D canvas generated with...
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