Is there a simple way to convert Flat Nets to Ports? I have a design without hierarchy and I want to add it.
Currently I have to do one net at a time which takes too much time.
Thanks
Converting Flat Nets To Ports
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How to edit text in model editor?
Sir/Ma'am,
I am new to cadence and PCB design software so please bear with me if this is something simple.
How do I get rid of the following errors:
**** EXPANSION OF SUBCIRCUIT X_D35 ****
X_D35.D1 N17008 N02077 X_D35.default
.model X_D35.default diode
---------------------$
ERROR -- Invalid model type
**** EXPANSION OF SUBCIRCUIT X_D37 ****
X_D37.D1 N17008 N02895 X_D37.default
.model X_D37.default diode
---------------------$
ERROR -- Invalid model type
**** EXPANSION OF SUBCIRCUIT X_D40 ****
X_D40.D1 N02882 N17184 X_D40.default
.model X_D40.default diode
---------------------$
ERROR -- Invalid model type
**** EXPANSION OF SUBCIRCUIT X_D42 ****
X_D42.D1 N02872 N17184 X_D42.default
.model X_D42.default diode
---------------------$
ERROR -- Invalid model type
ERROR -- Model default used by X_D35.D1 is undefined
ERROR -- Model default used by X_D37.D1 is undefined
ERROR -- Model default used by X_D40.D1 is undefined
ERROR -- Model default used by X_D42.D1 is undefined
I got a spice model for the diode in question from the company's website and ran it through model editor to change the voltage values to match the diode I specifically needed. (the spice file they had online was a "cure-all" for a number of diodes and had the values of a 'weaker' diode). I also changed it so I only had 2 pins (anode and cathode) in the model editor text file. I then output a .olb file and changed the shape of it in the designer. Then added the library file to my design to add the model. I did change the shape to resemble a zener diode. I deleted the "area and 't'" values because I only want 1 input and 1 output. I also edited my simulation settings>configuration files to include the .lib file to the profile.
This is the ORIGINAL text file:
.SUBCKT SMAJ4739A J S area=1 t=25
D1 J S default area=area t=t
.model default diode level = 1
+ IS=5p
+ N=1.0
+ RS=0
+ EG=.70
+ CJO=900p
+ M=.50
+ VJ=1.0
+ IBV=0.028
+ BV=9.0
+ TT=270n
.ENDS SMAJ4739A
This is what I changed it to:
.SUBCKT SMAJ4744A J S
D1 J S
.model default diode level = 1
+ IS=5p
+ N=1.0
+ RS=0
+ EG=.70
+ CJO=900p
+ M=.50
+ VJ=1.0
+ IBV=0.028
+ BV=15.0
+ TT=270n
.ENDS SMAJ4744A
I have tried looking for solutions but can't seem to get anywhere. Any advice/ideas are greatly appreciated.
Thank-you in advance.
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use dynamic copper and Cut out
Hi
I've some qustion.... I am not good English writing...
PCB editorwhen applying thedynamic shape atthePlate Hole
"HERE" such as the option of creatingthis??
- negative plane
- I'd like toseecheckedeasily.
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PCB prototyping
Hi,
I am interested to understand why is it that the currently commercial PCB prototyping tools (fast CNC, printers etc.) are not so widely adopted by the designers' community, the idea seems good so what stops it becoming part of the design process? what are the limitations?
Has anyone tried this?!
Thanks!
G.![]()
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Copying and pasting same circuit block layout in Allegro PCB-16.2
Dear All,
I have a circuit block that is repeated 10 times.
I have drawn it in Orcad capture by copying and pasting 10 times.
I did the lay-out of the block in Allegro-PCB editor.
Now when I am copying the block, the Ref-Des of the symbols are not getting updated ( showing *) and a lot of DRC errors are coming.
Basically there is no correspondence between circuit block in Orcad-Capture & the copied circuit block PCB layout editor.
Can anybody please tell how it can be achieved by copy & pasting. I don't want to draw the same layout 10 times.
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[ALLEGRO] "Place replicate" grid issue
Hi!
Can you please help me with understanding how aligning to the grid works when I use the "place replicate" functionality?
For example: I have two capacitors in SMD package I put them on the layout and they are aligned fine (I mean capacitors center points are aligned to the 5mils grid). But after I create the "Place replicate create" and move the group to another place capacitors centers are out of the grid. What options should I use to avoid the misaligment? Maybe Allegro is rounding off some values or something?
Regards,
Krzysztof
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Eye Diagram Parameters in SigWave Script
I've created a PERL script to generate a SigWave script to display selected waveforms. One of the attributes that I control with it is putting SigWave into eye diagram mode and setting the parameters. For instance:
setwindow main
graph mode eye
eye diagram params -clockfreq "200MHz"
eye diagram params -clockstart "10ns"
The above script fragment sets eye diagram mode and some parameters in the "Eye Diagram Preferences" menu. I would also like to control the number of eyes displayed in that menu, but I cannot find the parameter name that controls that setting. I've tried "recording" a script to see what happens when I set the number of eyes, but it is not captured in the recording (neither is the "clockstart" parameter - I discovered that one accidentally).
Does anyone know the parameter name to set the number of eyes?
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Benefits of converting PCB files to gerber files
Generally, pcb design
engineers is used to sending PCB format files or just output PCB files from PCB design software to the pcb manufacturing factory, sometimes this will bring some
trouble and risk since PCB manufacturer need to convert PCB files to drilling
files and Gerber files for production.![]()
Because electronic engineers and PCB engineers have different understanding of PCB board, Gerber files converted by pcb factory may not be exactly what customer want, for example, you may define parameters of the components in the PCB files while designing a PCB board, but you didn't indicate that you do not want to put these parameters on the final PCB boards, PCB factory will follow the PCB files completely to produce PCB with all these parameters on the final pcb product. If you convert PCB files to GERBER files by yourself will avoid such trouble.
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Diff pair to diff pair spacing based on their vias?
For forever and a day I've been able to manage pair-to-pair spacings without any effort. Allegro conveniently stores the primary gap spacing with the physical rules, so this has always been a breeze. But now, I'm being asked to base my pair-to-pair spacings on their vias instead.
Is there an easier approach to this other than putting each diff pair into their own net class? No matter how I slice it and dice it, It seems that a "DPr"object will pass on its rules to its individual nets.
Thanks
Eric
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Z-Copy Shapes
All,
I'm trying to z-copy shapes. I have 4 sucessful layers where I fail to creat shapes on AGND\PGND & PGND|DGND. I use the same procedure, what am I doing wrong or stupidly?
-Ron Scott
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Model of LM1893
hello,
can you help me to find a model simulation of LM1893 component in Pspice? or method to simulate the schema that exists in the PSpice library Analog2 .
thank you![]()
can you help me to find a model simulation of LM1893 component in Pspice? or method to simulate the schema that exists in the PSpice library Analog2 .
thank you
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inductor symbol
Dear all,
In Orcad 9.2 how i will place inductor symbol in SS(silkscreen), and their is any indcutor libraries available in internet or not. Give some ideas...
thank you
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Capture not able to generate pcb editor netlist files
Whwn I prepare any project in orcad capture and then create netlist for the Pcb Editor and i chose the option to open the board file in allegro pcb editor . When i click ok it just displays the message that the project will be saved prior to netlisting and i chose ok.
After it nothing happens . no files are generated and PCB Editor does not open. I have added the allegro.cfg file in setup option.
The design is ok.
Help Me Please????
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IPC-7351B
All,
I tried following the directions in th CD and it didn't work. Anyone here have the magic sauce? It's telling me to install in these directories:
These files must be manually copied to either the following folders (depending on your computer's operating system):
C:\Program Files (x86)\PCB Libraries\FPX 2012\Libraries
C:\Program Files\PCB Libraries\FPX 2012\Libraries
These to be installed:
BGA_2012.fpx
SM_2012.fpx
TH_2012.fpx
Thanks,
Ron Scott
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Script/Source files nested too deeply
After I installed Cadence 16.5 on one of our machine and when I try to open it I got this error (see below image) –any suggestion?
Script/Source files nested too deeply
Unable to find the messaging system module definitions file 'allegro_smi_modules.txt'
ERROR: Could not initialize the Allegro error messaging system
Also tried from the old post --renaming PCBENV didn't work, and uninstalling Allegroviewer and reinstalling didn't work. Uninstalling Allegroviewer, deleting the PCBENV folder and then reinstalling Allegroviewer did NOT work eitherThanks,
Patrick ↧
How to select all the shapes & traces efficiently in "Place & Replicate" option in Allegro 16.6
Dear All,
I am using Place & Replicate option to create a Module which can be later used for replicating layout-blocks in Allegro-16.6.
When I am clicking "Place & Replicate create" after selcting the symbols desired to be in the module, it is asking for selcting the shapes.
My Module is fairly complex having a lot of shapes and traces. Selcting each shape by clicking Mouses is fairly tedious.
Can anybody please tell how one can efficiently select the shapes and traces so that there will be no need to have cliks on each shapes.
Kind Regards,
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DRC error in pcb editor
hi every one, i have a problem when i have DRC check in pcb editor , the error is: line to thru pin spacing
it takes on my regulator ( LM2676)
how can i fix it?
thanks
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[ALLEGRO] Constraint regions under BGA
Hi,
I have to you the following question: I have two different Physical Classes. One is e.g. for 100Ohm diff pairs and the other one is for 50Ohm single ended lines. Let's say that diff pairs are 5 mils with 5mils spacing and that 50Ohm is 7mils. How can I now create the classes under the BGA so that the diff pair will be resized to the 4 mils tracks with 4 mils spacing and 50Ohm single will be resized to 5mils?
Regards,
Krzysztof
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Unsupported Prototype message when moving component
I'm new to this software, and recently this new thing that has started happening on my design, but when I try and mvoe a component, I get the pop up for:
"This is an unsupported prototype level funtionality.... "Slide etch" is an alternative to "Stretch etch" for maintaining connections to pins and vias that are being moved."
I'm not sure why it's coming up. I erased all of my traces and planes because I need to do some significant changes, I can't grab any etch on the componens pins, so I don't know why it's trying to do anything but move it. Happens in both General and Placmenet modes. Thoughts?
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ODB++
All,
When running ODB++ on a board that is DRC clean, I get a message that "translation failed " and then the open viewer failed, File continues on and it does generate a .tgz What's a solution to this problem?
Ron Scott
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