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Default Drawing Properties

June 5, 2018, 11:32 am
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We have noticed recently that there are a few default drawing properties that are being attached to the .dra when created from scratch.  Can anyone tell me where these properties can be configured and turned off in a configuration file? 

The properties we are see are

MECH_PIN_TO_CONDUCTOR_SPACING = 0.203 MM

   MECH_PIN_TO_MECH_PIN_SPACING = 0.203 MM

We know the properties are set in the Constraint Manager -> Analyze -> Analysis Mode -> Design -> General but don't know why they are coming in by default.



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3D Canvas Export

June 6, 2018, 6:48 am
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Hello,

I am a newbie w/ SPB17.2 and latest hotfix.

When looking at 3D canvas, I see the symbols with the step file shapes that were mapped to them.

When I export (step and 3D pdf so far) all I get is the volume of the place bound, if any.

I don't see any related options in 3D canvas itself.

How can I export what I see in 3D canvas?

Thanks,

Emmett

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How to create Homogeneous packages in Allegro Concept HDL

June 7, 2018, 2:51 am
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Hi,

I am using allegro concept HDL 16.6. In part developer, i want to create homogeneous package having 4 function slots S1-S4 with pin names from A1- A4. When i give pin numbering from 1 to 16 and generate symbol, i can see only one symbol created with 4 pins A1- A4 . The other three symbols for slots S2-S3 will not get created. How to overcome this (or) is there any other steps to be followed to create a homogeneous package.

Because i am able to create Heterogeneous packages without any issues.

Kindly help me with this issue.

Regards,

Chadga

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Thermal Pad Spoke Angle

June 7, 2018, 8:19 am
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Hello,

I am a newbie to SPB17.2 w/ latest hotfix.

I have created the padstacks that I need for my 1st PCB.

I used a circle for the thermal pad and not a flash symbol.

When I pour copper, the spokes are vertical and horizontal.

I would prefer 45° angles (better for tightly spaced arrays of pads).

Is there a global setting or anything?

Thanks,

Emmett

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How to Select Only Wires or Nets in Area in Schematic

June 8, 2018, 1:05 pm
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Specifically in Design Entry CIS (17.2 S037), I can't find a setting that allows me to only select net wires in an area.  I'm trying to quickly select all nets in an area to apply a net_physical_type and net_spacing_type net class attribute to these selected nets.

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Create Netlist renames nets instead of changing reference designators.

June 9, 2018, 9:43 am
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I have a design that has schematic changes . Unfortunately they also changed a number of reference designators for identical circuits . It looks like the ECO process does not have an option to change reference designators first then net names. The software just changes net names to match the net netlist. Is there any way to get around this problem  ?

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Easy way to manage footprints and padstack libraries

June 10, 2018, 5:18 am
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Each of my projects is different from others in terms of pcb foortprints despite the components names could be equal. Is there any way to assign footprints to parts in terms of projects and not adding paths in PCB Editor for each new project? for example like it's done in Altium - i create a project, assign all the footprints and it's done so that i have specific library for each project containing parts, footprints etc.

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Crefer data is not visible on schematic page

June 11, 2018, 5:33 am
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HI,

I am using Allegro Concept HDL 16.6 version. I have created design having two pages and connected the pages using OFFPAGE connector( IN and OUT). I have given the same signal names as well. i am able to generate the Crefer without any error, but the Crefer data is not visible in the schematic pages near the ports as to which page the signal is going. 

Kindly help me on this issue.

i have attached the screenshots for more information.

Chadga.

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Unable to complete the loop of ECAD-MCAD collaboration using IDX format in 17.2

June 12, 2018, 6:24 am
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Is anybody using the IDX format?  We have used IDF for years, but are starting to transition to IDX.  We did testing using 16.6, and after a few bumps were smoothed out, we thought we had the process down.  The projects we started to use it with happened to be 17.2 designs, but that shouldn't have been a problem.  What we found was that 17.2 is unable to import MCAD acceptances of changes made by ECAD, so the propose-accept loop of the IDX process cannot be completed.

  • We started with a baseline in Creo, saved to IDX and imported the holes, outline, areas into Allegro.
  • Components were added in Allegro and exported as an incremental IDX.  These changes were "additions".
  • The IDX is opened in Creo, the changes accepted, and the accepted status saved in the IDX.
  • Importing the IDX back into Allegro is supposed to mark the transactions as accepted in the BRD, but Allegro states "No change to process. The following are up to date: 1. MCAD's proposed transactions. 2. ECAD's approved or rejected transactions."
  • So, if another change is made to any of those components that were already accepted into Creo (but not recorded as accepted in Allegro), the new change is exported as an "addition" again, and Creo can't import because the component already exists! 

Has anyone else experienced this? Have a work around? We opened a case with Cadence, and they've submitted it as a bug report, but don't know how quickly a resolution would be found.

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Can i create a capture schematic by pspice netlist

June 12, 2018, 11:09 am
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Hi everyone

I wish to find a way to import a text format into capture other than design xml. There is an option to create pspice netlist. but what does it do? i can only read it? PCB editor takes a netlist, generating everything with few clicks. Does the pspice netlist do the same thing?

Thanks

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Free Gerber AND Drill-data viewer?

June 13, 2018, 5:37 am
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I have a habit of always wanting to make a check of the generated Gerber files

to see that what I wanted to be included really is there. For many years I have been using Pentalogix ViewMate

knowing that this viewer has never been able to display the drill data (.DRL) in a correct scale visavi

the artwork.

The other day, I got a comment from a co-worker who also complained about this and then I remembered

why I never bother to even try displaying the drill files.

I would like to use a free independent viewer that can do this.

Any suggestions? 

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Do the new Rigid-Flex features of 17.2 version of PCB Editor require a special license?

June 13, 2018, 11:07 am
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Hello all,

I'm currently evaluating the new 17.2 version of PCB Editor, and I'm using the same Allegro licenses that I was using for the 16.6 version: Allegro PCB Designer, High Speed option and Miniaturization option.

I'm being able to use some of the new Rigid-Flex features. I can add all the flex layers in the new XSection window (Coverlay, Stiffener, Adhesive and Soldermask Layers).

However, I don't have the Zones option available in the Setup top pull-down menu. Please, see picture below:

 

I guess it’s probably because I don’t have the license required to use all the Rigid-Flex features. The Zones option opens windows in which different stack-ups created in the XSection window are assigned to different regions in the design.

Can anybody inform if it requires a new Allegro license option to enable the use of all the Rigid-Flex features?

Any help will be appreciated,

Thanks!

Gustavo

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Eagle -> Allegro 17.2 Translation, Redefine trace signal

June 14, 2018, 6:23 am
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I have translated a large board from Eagle to Cadence PCB 17.2. The board used Blind/Buried Vias which were not translated into Cadence. The traces which connected to these Vias were all renamed to GND during translation. Is there an easy way to select individual traces and redefine them back to their proper signal?

Thanks,

Andrew

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Can I shrink an imported schematic?

June 14, 2018, 11:46 am
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I took advantage of TI's online WEBENCH tool to generate a schematic for a voltage regulator circuit.  The tool provides an EDIF and a configuration file.  These are imported into OrCAD (17.2).

The resulting schematic is *huge*, with each symbol being 2 - 3x larger in height and width than a symbol that you would drop in the design using Add Component.  I need to use a D-size or E-size sheet to accommodate a modest design on 20 symbols (almost all resistors or capacitors) and anything that I add to the new sheet appears miniscule.

Is there any way to do a wholesale shrink of the imported schematic?  The symbols each contain a lot of information, so redoing it from scratch is not really an option.  Thank you.

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3d convas board shape not coming

June 15, 2018, 2:16 am
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hi every one

 In 3d convas 3d viewer board shape not coming exactly. like arcs board cuttings slots. what is problem please help me 

Thanks,

Balaji.j 

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Remove footprint properties

June 15, 2018, 12:02 pm
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When creating BGA footprints, we used the package symbol wizard with the default template.  These symbols now have several properties that are not in the symbols that we created manually:

  • Physical_Contstraint_Set=Default
  • Same_Net_Spacing_Constraint_Set=Default
  • Spacing_Constraint_Set=Default

How can I remove these properties?

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Flex PCB - Zones Definition in Gerbers

June 18, 2018, 12:09 pm
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I"m having difficulty finding any documentation on the best way to communicate flex pcb zones in my gerber files to the manufacturer.  I'm thinking I might create another film and just add the zone information to it.  Does anybody have any suggestions on the proper way to do this?

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Only include PDF export properties

June 18, 2018, 1:44 pm
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Hey Everyone,

There is a nifty feature in Capture CIS 17.2 that exports PDF (File > Export > PDF) with properties of the component like part numbers, manufacturer, voltage, etc. But there is only an "Exclude properties" option, Capture has a bunch of properties I would like to exclude but I would rather simply only include the ones I want instead. Is that a possibility?

Thx,

Aric

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adding vias to a part (symbol)

June 21, 2018, 2:19 pm
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Hi

I'm new to OrCAD and have only done one design so far but I'm trying to figure out how to stick vias into a thermal pad.  I have a QFN design from a friend and I can't tell if he did it as well but I've seen the board it created and he's got tented vias in the thermal pad and I can see from the design files that he's got the solder mask in a pattern and paste mask in a pattern so there's a clear place where the vias go but I don't see them on the package when I open it for edit.  Is there a way to do this or is it done when you're creating the board or was it somehow included into the package pin but I'm not seeing it when I open up the padstack editor?

Thanks

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3D Viewer - Rotate

June 22, 2018, 8:26 am
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I'm starting to play with the new 3D Viewer.  How do I view the other side of my PCB in isometric view?  It looks to only show an isometric Top side and I want to see the an isometric Bottom side.  Or at a minimum be able to actively rotate the design.

Thanks.

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