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Skill files location

February 19, 2009, 1:09 am
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Hi,

For running skill files, is there any way to run skill files from one location.

currently I have to copy skill file in my working dir and then I load it and then I am able to run it.

actually I want to make aliases for skills which we use frequently, when I make script of loading skill file and asign it in aliases it is not working because it needs to have skill file in the working dir. I dont want to copy skill files in my working dir.

If any one knows please tell me the procedure.

Thanx & Regards

Tanveer

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Routing differential pair with same length

January 10, 2013, 2:26 am
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I am trying to route a differential pair, but I am having trouble making each trace the same length. Is there an easy way to do this in allegro?
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Design Entry HDL grid errors

January 10, 2013, 7:37 am
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 I have been trying to build a schematic and the grids are not loading properly.

 Under Tool, Options, Grids, I have set my grid to Decimal, Show Logic Grid - On, Size 0.025, Multiple 1.

But the console show my grid as size 0.024  1.

When I check the grid size I have dots at 0.012 pitch.???????

Can anyone enlighten as to why the grids are nothing like those required. And the components will not lock on the correct grid to make a clean schematic.

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Need someone to convert PADS to Allegro successfully

January 10, 2013, 9:02 am
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 I have a design to modify, unfortunately the original is in PADS 9.3.  I have Allegro 16.0 and having lots of problems trying to get it to load.

Anyone out there done this before and got it to work?  I can send the files (asc).... one is PCB and the other the schematic.

I am willing to pay for a "good usable conversion for 16.0".  Anyone????

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anyone successfuly installed OrCAD Capture CIS 16.6 with CIP?

November 6, 2012, 11:59 am
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Our CIP schematic symbols are not showing up.  Just the ones in the supplied library.  Everything works fine in 16.3 but we are trying to get the upgrade done.

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Converting the Layout Libray 9.2 to Allegro PCb Editor 16.3??

January 11, 2013, 12:25 am
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Hi.

I am using the OrCAD 16.3. Me had worked fully with layout 9.2. But in my organization they told that use the Allegro PCB editor except of layout 9.2. 

My Problem is i want to convert my library files of layout 9.2 to allegro PCB editor 16.3.Later some time me had tried the conversion of files in layout 16.0 too.That also been get worked.So me need the details of converting the library files OrCAD 9.2 to OrCAD 16.3 files.

So provide me an better solution to do this. Because my library are too larger to create it.So only.

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Re-using design constraints with different stackups.

January 11, 2013, 9:17 am
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Hello,

      Is there a way to re-use design constraints if the stack-ups are different?  I just finished a 12 layer board and am now working on an 8 layer board which requires the same constraints? Ultimately all I would like to transfer is the spacing constraints. Is this possible? Any help would be greatly appreciated.

Thanks,

Clint

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Stacked Via Constraint Control (Performance L Option)

January 10, 2013, 3:59 pm
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Hello,

       I am currently working on a design that shall utilize stacked micro vias from 1 to 4 with a buried mechanical from 4 to 5 followed by stacked micro vias from 5 to 8.  We cannot stack on the buried mechanical from Layer 4 to 5 and the micro's must be offset from it.  Is it possible to adjust the constraint manager to allow the micro's to be stacked and only apply the offset to the mechanical with the Performance L Option? 

       When I adjust the Min BB Via stagger value it applies the offset to the entire stack.  When I created the padstacks for the vias I checked the radio button for Micro Via's and did not for the burried mechanical. I was hoping this was a flag to the CM but I assume it is not. Any help would be appreciated.

Thanks,

Clint 

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Creating a WEEE wheelie bin logo with logomaker

January 11, 2013, 6:57 am
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Hi,

I'm trying to make a WEEE logo with logomaker, it is importing ok, but I'm just getting the outline of parts that should be solid, for example the black bar at the bottom and the cross.

Is there a way of changing this?

Thanks, 

Graham 

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Defining grid Problem?

January 11, 2013, 9:40 pm
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Hi..

I had kept the grid size of Non etch as 0.127mm and Etch also 0.127mm. But when i give OK command means the etch gird values are get vanished from it. I don't know why??

Can anyone provide me the solution.

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Issue updating symbols in PCB Editor

January 14, 2013, 11:39 am
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 I have an issue (version 16.5) where I had to upgrade a component and add a pin to it.  But the schematic netlisting function appears to ignore this, when I try to quick place the component I get: 

"ERROR(SPMHGE-82): Pin numbers do not match between symbol and component. Run dev_check on device file for more information."

 From this issue and another one I found on the same BRD file, it appears once I have a symbol in the BRD database, I am unable to remove it.  If I rename the symbol to another name, it works fine and that is what I plan to do, but I do think this is a problem with the tool.  Is there a similar function for the BRD file that you can do for the schematic file where you "Clean up the Cache"?

I noticed that if I have a mismatch between the symbol version in the Database and in the Library, the library component will not appear.  I don't know if this is supposed to happen, but it prevents me from manually upgrading my symbol.

 I have searched many of the other posts concerning similar problems and I tried several of the indicated suggestions, with no improvement.

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Without opening Capture CIS, listing of symbol names in library?

January 14, 2013, 1:21 pm
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Is there a utility or secret trick that accomplishes this?

Looking for a way to script the discovery of CIS parts that use invalid symbol names.

Happy to periodically dump the listing to a file and work off of an ascii file.

Thanks.

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Silk Screen Visibility OrCAD PCB Designer 16.6

January 3, 2013, 10:48 am
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I've opened up an existing brd file that I generated using OrCAD PCB Designer Professional v16.5.  It appears that all of my parameters remained intact, however, the colors, transparency and brightness of the individual elements look different.  Most of the differences aren't bad, they're just different.

 The only problem I'm experiencing with this new color scheme is that my silk screen elements are almost completely invisible.  You can't really see them unless you place your cursor over the silk screen element that you would like to see.  I've even set the color of all of my silk screen elements to bright white in the Color192 screen and toyed with the transparency and shadow settings.  The only way I can see the silk screen items is to supress all of the other elements and just enable the silk screen stuff.  Even then, the color of the silk screen stuff is very muted and not very bright at all. 

Has anyone else seen this or have an idea how to make the silk screen more visible or brighter? 

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need help

January 14, 2013, 4:10 pm
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SPCOCN 1158

January 15, 2013, 12:48 am
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Hi ,

 

im using Allegro Design Entry HDL 16.5 , while Im trying to save the design Im getting an Error SPOCN 1158

 "failing to open intermediate file "  page1.csb

Does anyone know how to solve this

 Regards,

 

Avi  

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PCB DESIGN IN ALLEGRO

January 15, 2013, 2:34 am
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What 's  the different between allegro pcb design GXL and allegro pcb XL,When  start the software? 

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Net names and illegal characters

January 14, 2013, 1:09 pm
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In our previous designs I would append a \\ to the end of a net alias to signify that it is active low. Example; OUTPUT ENABLE\\

Now I find that the "\\" is considered an illegal character so I have two questions

1. I'm open for suggestions as to a different approach on how to show that the net is active low within the net alias

2. Is there a way to catch these "illegal net names" in Capture before I go and import the logic into PCB Editor. I have run all sorts of error checking in capture and these nets do not come up as being problems.

Tom

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OrCAD PCB Designer 16.6 Dynamic Fill Question

January 15, 2013, 6:12 am
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I've included a copper ground plane on a board I'm working on.  I'd like to "hide" the copper plane while I'm routing.  I thought I could do this by selecting the shape and selecting "defer performing dynamic fill" in the Options panel.  When I click "defer performing dynamic fill" the copper plane disappears, as I suspected that it might.  However, when I click "Done", the plane comes back.  How do I hide just the copper plane without hiding my clines, vias or other features on that etch layer that I want to see?

 I'm sure there's gotta be a simple solution to this - I just can't find it. 

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Library Construction in Allegro and Design Entry HDL

January 15, 2013, 8:24 am
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 I have used OrCad Capture CIS and Layout before and the library system was fairly easy to follow. But I now need to use Allegro and Design Entry HDL for part creation

Can anyone tell me how the library structure is set out in these systems please. Where are footprints and schematic symbols stored within the library structure.

I need to create local ptf files, footprints and symbols. How are these stored? Is there a prefixed set-up.

Any help would be greatly received.

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Design Entry HDL grid errors

January 10, 2013, 7:37 am
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 I have been trying to build a schematic and the grids are not loading properly.

 Under Tool, Options, Grids, I have set my grid to Decimal, Show Logic Grid - On, Size 0.025, Multiple 1.

But the console show my grid as size 0.024  1.

When I check the grid size I have dots at 0.012 pitch.???????

Can anyone enlighten as to why the grids are nothing like those required. And the components will not lock on the correct grid to make a clean schematic.

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