Changing multiple pin text names

April 16, 2021, 11:33 am

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Hi all, first time to post here.  Is there a way in where I can easily change pin text names in one shot (bring up a list, change it from before to after) and then have Cadence add those pin text names instead of changing them one at a time?  I created a 135 pin BGA footprint but my array names (A1, A2, etc.) were supposed to be in a vertical column (top to bottom), not horizontal (left to right).  It would take me forever to change them one at a time. 

In the schematic editor, this is easily done as you can edit pin names and pin numbers.  I was wondering if you can do the same in the footprint environment.  Thanks in advanced!!  

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How to add symmetric ground reference via in PCB editor 17.4?

April 17, 2021, 8:30 am

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My intention is to add reference ground return via for PCIe3 signal. The following image is the one I have added and it is not symmetric. The other image is the reference board layout, it is how my desired out should be.

Any advice on how to update my layout?

My non-symmetric layout:

Desired output in the reference design:

DRC report window disappeared

April 18, 2021, 6:22 am

≫ Next: If you need to dynamically assign nets to a connector or FPGA during routing and update the schematic. I shared a Skill script.

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Hi, 

I'm using Orcad Capture 16.5. 

for some reason, while running DRC, I stopped seeing the report in the bottom of the screen, and instead, I have to go to the *.DRC* output file in some directory. 

how do I make the window that used to show the report quickly appear again?

Thanks

If you need to dynamically assign nets to a connector or FPGA during routing and update the schematic. I shared a Skill script.

April 18, 2021, 5:35 pm

≫ Next: The right way to go with Place Replicate

≪ Previous: DRC report window disappeared

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https://community.cadence.com/cadence_technology_forums/f/pcb-skill/47891/skill-method-to-optimize-netlist-pin-assignments-on-components-in-allegro-and-orcad-capture

The right way to go with Place Replicate

April 19, 2021, 8:54 am

≫ Next: Can not select/move multiple elements

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What is the "right way" to go with Place Replicate? Is there a preferred workflow when using Place Replicate?

I've only seen tutorials/videos on how to use them in the PCB Editor, but it seems more logical to define a Replicate Module in the schematics instead of clicking and selecting symbols in the PCB editor. Can that be done?

Also, how can I view existing Replicate Modules? I get the below message when trying to create a place replicate module. Is there an editor where I can edit existing modules?

Can not select/move multiple elements

April 19, 2021, 3:29 pm

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Greetings,

First time when selecting multiple elements in OrCAD Capture and trying moving them in PCB, works like expected. Problem occurs everytime after that, where instead of moving all selected elements I can only move one or two. 

I have Intertool Communication enabled.

After I save PCB, I can select and move multiple elements again(once).

Any advice?

Thank you for your answers.

Regards,

Brane

How to check maximum copy usage of license in history?

April 19, 2021, 6:24 pm

≫ Next: Castellated Holes 0.55mm pitch

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Hi All,

Is there any way to check how many people use license by time or by day?

I don't know how to find the log file for license usage

the LMTOOLS seems like supporting only simultaneous access at the session window

regard

Castellated Holes 0.55mm pitch

April 20, 2021, 2:38 am

≫ Next: See all parts/off-page connectors connected to the schematic net

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Hi I want to design castellated holes on my very small PCB(13X10mm). There will be total 28 such holes with 14 on each side of PCB. 

The pitch between holes is 0.55mm. So, we are bound to have 0.25mm diameter of these holes and pad size could be 0.3mm.

An example showing illustration(not actual PCB):

The approach would be to place rectangular pads(0.3x 1/1.5mm) with 0.25mm holes on the edge of PCB and let manufacturer cut these pads in half. Or any other inputs?

I am wondering if this small pitch would be problem or is pretty standard?

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See all parts/off-page connectors connected to the schematic net

April 20, 2021, 5:25 am

≫ Next: Allegro DE HDL Ports use

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Hi all,

I work on cable schematics creating and have sometimes to connect 300+ pins between 2 connectors. We work with off-page connectors as pins in the connector and connector shell on schematics it is just graphic square.

I wanted to know if it possible to see somehow what off-page connectors is connected to the same net in the schematics and also if there is a command that can do it to help me in writing the macro?

For example I have connector P1, pins 1,5,7 of the connectors is named P1-1, P1-5, P1-7. They are connected to the same pin in connector P3 to pin P3-4.

When I click twice on the net I can see only 1 name P1-1 in the field, but if I click on the field I can choose  P1-1, P1-5, P1-7, P3-4.

Now, what I want to get is list of the names: P1-1, P1-5, P1-7, P3-4 and it's how I will know that all 4 pins is connected to the same net.

After I got all that groups I can go back to the excel file and compare to it.

Allegro DE HDL Ports use

April 21, 2021, 9:17 am

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I have a number of 'open drain' output devices on different pages and need to use output ports for a multi-level schematic. But I keep getting complaints as there are multiple 'outport' s being used.

Is there a better port to use instead of 'output'?

My schematic ports shows an 'aoutport' and 'bufport', also and 'offpage' port! Which of these are a better output page port?

How to verify unwanted symbols modifications?

April 22, 2021, 1:42 am

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Good day,
I work with OrCAD PCB Editor version 16.6. I want to verify the PCB design after someone else. I don't know how to find out if the symbols from the prescribed company library were used for all components. Whether there was unwanted symbol modifications. How to do it?

Thanks,

Michal

Set different width for same trace

April 22, 2021, 5:57 am

≫ Next: Part Sectioning in DE HDL and displaying

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Hi,

I want to connect Data pins of the IC to the data pins of the USB and want the width of that trace to be 15mils. But problem is IC  and USB  pins can connect only 10 mil trace width otherwise it gives error.

Can we change the width of the trace in between ? If yes, can anyone please help me how to do that ??

Thanks

Part Sectioning in DE HDL and displaying

April 22, 2021, 9:15 am

≫ Next: How to convert SIMPLIS model to Pspice model? is it available?

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When creating/using dual or quad parts. Each new part has it's own section. IE, U2 section 1, U2 section2 etc.

In the past, these are displayed in any other CAD software as U2a, U2b etc. so you can see clearly that they are multi-sectioned parts. But DE HDL doesn't allow for the lower case letter on the sections? Why? How can we get the section numbers to display properly on these parts?

How to convert SIMPLIS model to Pspice model? is it available?

April 22, 2021, 6:26 pm

≫ Next: Trimming specific shape refer to other layer shape

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Hi All

as I know, Pspice library is available to convert to SIMPLIS model

then Is it available to convert the SIMPLIS model to Pspice model? 

regard

Trimming specific shape refer to other layer shape

April 22, 2021, 10:34 pm

≫ Next: How to control "Same net spacing" constraint rule value of overlap rate?

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Hi All

there is 2 different layer shapes, the one shape is made by following the Cline of +12V net which is highlighted (red color), the other is large GND net (yellow)

I want to cut the red shape refer to the yellow shape boundary. I tried to cut using Shape Operations function, but it didn't do well that I want

that is just sample test, actual board that I design has quite complex shape (not retangle) so I need that function.

Is there any good way to solve this problem?

regard.

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How to control "Same net spacing" constraint rule value of overlap rate?

April 22, 2021, 11:33 pm

≫ Next: PSpice simulation error (ORCOMMN-2302)

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Hi All

If I actvate the same net spacing rule at the analysis mode, the same nets between Via and Shape keep the distance per overlap rate.

as I know from the test, the via only applied the rule with same net shape under 50% overlap rate.

but I want to keep short net the via with shape even under 30%. (see below)

of course it is working without activating same net spacing rule, but I have to keep on the rule..

how can I control the rate value of this?

regard

PSpice simulation error (ORCOMMN-2302)

April 26, 2021, 6:36 am

≫ Next: how to delete unused nclegend subclasses from copied board file?

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I downloaded the SPICE file of GaN HEMT from the website of GANSYSTEM and generated the simulation file. The error as shown in the figure occurred while I using PSPICE simulation. I hope I can get someone‘s help, thanks.

how to delete unused nclegend subclasses from copied board file?

April 26, 2021, 8:56 am

≫ Next: IPC-2581 import - not seeing nets or components

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Is it possible to delete unused nclegend subclasses from copied board file?

IPC-2581 import - not seeing nets or components

April 26, 2021, 9:35 am

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I exported an IPC-2581B file. The nets and component boxes are checked. 

I imported the IPC-2581B file into a new board layout. What I see looks like Gerbers. I don't see any nets or component information.

Is this normal, or I am doing something wrong?

Can't Open OrCad PCB Editor

April 7, 2021, 11:21 am

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I am unable to open OrCAD PCB Editor application at all. Each time I try to open, I get the following message.

I've recovered the .SAV file to a .brd using DBDoctor, but that did not fix it. I've updated from S015 to S016. I've tried other board files. Nothing works. 

Ideas on how to open the program?