strange Design Compare behavior

 Hello,

 this is really strange to me,  I am using orcad 16.6,  I have an old layout design, there is a LED pin 2 ( D13.2) connected to ground. 

 for the pstxnet.dat file, under 

 NET_NAME 'GND'

................................................................................................

NODE_NAME    D13 2
 '@TOL-1371_SCH_R01.CONTROL MODULE(SCH_1):CONTROLLER BOARD@TOL-1371_SCH_R01.C1-CONTROLLER BOARD(SCH_1):MAIN CONTROLLER@TOL-1371_SCH_R01.C2-MAIN CONTROLLER(SCH_1):INS17176580@DISCRETE.LED.NORMAL(CHIPS)':
 'CATHODE':;

after I modified the design and clean up the liberary, the LED pin 2 still connected to ground. for new pstxnet.dat file,

NET_NAME
'GND'
 

.......................

NODE_NAME    D13 2
 '@TOL-1469.SCH, REV 01 SCH, SERENITY IV DEVELOPMENT BD.CONTROL MODULE(SCH_1):CONTROLLER BOARD@TOL-1469.SCH, REV 01 SCH, SERENITY IV DEVELOPMENT BD.C1-CONTROLLER BOARD(SCH_1):MAIN CONTROLLER@TOL-1469.SCH, REV 01 SCH, SERENITY IV DEVELOPMENT BD.C2-MAIN CONTROLLER(SCH_1):INS17176580@LED.LED_2.NORMAL(CHIPS)':
 'CATHODE':;
 

 the layout is based on old schematic. and  use import logic to update the net list to new desing. 

if I check the Design Compare for either old or new deisgn only, the D13.2 is in net GND, see following screen catch. but if I compare the old and new design together. the new design ( left side of the compare result) become D13.1, last screen catch. 

 something must be wrong. couldn't figure out. 

any suggestions are appreciate.

thanks,

David