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Vias in a symbol
I have a new dilemma this morning. I have an array of 30 vias that I need to embed in the tab of a TO package. My first curse of action was to add the VIA at the board. This led to inconsistent hookup...
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Boundary
Gents,I might be missing something painfully obvious but if you refer to the atached pict, I need to make a PLACE_TOP_BOUNDARY and I need to hold to it's shape. I started out by putting in rectangle...
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Fillets(teardrops)
Folks,I'm trapped working with a bunch of mechanical engineers that have a penchant to implementing everything they read. My latest battle is that the MEs have read about fillets and want to utilize...
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Create Via library
Gents,I have been using a via set for years that will suit my needs. I'm sure every desigher here has there own set that fulfills thier requirements. Having said all that; to fulfill a request by my...
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need your help
I have been using Orcad 16.6, pcb editor for a while, everything works fine for me, I update license last week( add one more 16.6 licnese) . everything seems OK until I am trying to use artwork. after...
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Soldermask-to-Etch Clearance Check
I've set the spacing of "line to SMD Pin" to 0.5 millimeter as figure show below.But,don't konw somehow the DRC check can't detect the error that the Etch overlap with soldermask of SMD Pin,figure show...
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How to avoid adding hundreds of nets one by one
Hi experts, I am drawing a schematic with Capture, there are several large connectors in my schematic, I've already generated all nets needed in an excel, these nets are irregular. If I add these nets...
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3D STEP files
Folks,On the infrequent occassion that I have to deal with mechanical stuff, I have been able to generate IDF files and send them off to my mechanical to use. I have now a new requirements to supply...
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Importing ConceptHDL 16.6 schematic into ConceptHDL 16.3 design
I am looking to reuse some of the existing design with the new design with from a newer version of the software. How can this be done? Thanks
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PSPICE A/D - operations on two waveforms from two different simulations
I have two waveform: one V(I) at a temperature of -40°C and another one V(I) but at a different temperature, 85°C.How can I make a 3rd waveform by substracting the two mentioned?
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library pointer
Hi All,Running SPB16.6. My current lib path is:PSMPATH = . symbols .. ../symbols C:/Cadence/SPB_16.6/share/local/pcb/symbols...
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.drl file generation reg.
when generating NC drill file 'm getting the bellow error. WARNING: Design precision is greater than that of the drill output file data.Data rounding errors are very possible.ERROR: The number of...
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Hierarchical design
hi,i have created a hierarchical design with many schematics inside it. Now i have to make a pdf of the design. And there is an order in which the pdf should be generated.eg.pages in schematic folder...
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Routing over voids
Does Cadence have a function to help us indentify routing over voids and splits for high speed nets we care about? If yes, where can i find it?Thanks,Patrick
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Learning Allegro
There is any option available to learn allegro inbuilt? I found in Orcad, under help menu.But cadence not able to find.
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ERROR CAP0049
OrCAD CAPTURE 16.2It is about to become me crazy.The following popup shows up every time I click on anywhere inside my schematic.CAP0049Errors were detected while reading a page. Please, open the page...
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Create Via library
Gents,I have been using a via set for years that will suit my needs. I'm sure every desigher here has there own set that fulfills thier requirements. Having said all that; to fulfill a request by my...
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PCB Design with a Microcontroller (Orcad Layout/Capture/PSpice)
Ok, I'm not trying to actually simulate a microcontroller in Pspice. :)But, I have designed a simple circuit that has a microcontroller at the heart, and I wanted to use the PCB design features to...
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strange Design Compare behavior
Hello, this is really strange to me, I am using orcad 16.6, I have an old layout design, there is a LED pin 2 ( D13.2) connected to ground. for the pstxnet.dat file, under NET_NAME...
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