Hello,
I am new to the forum and new to Cadence as well. I have designed both a CMOS and BJT ROM and am trying to perform Gate level simulations with Cadence Allegro. My BJT ROM outputs show correct movement with the inputs, but my CMOS ROM stays at the 1 position for the entire simulation. Is there something special I need to do with my NMOS and PMOS gates to achieve functionality? I have used the Pspice components in Cadence Capture and am running mixed signal testing.
Any help would be greatly appreciated.
Thank you!