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Delete Module instance name

Hello I wanna array boards.But I un-hope to display instance name.Have anyone know how to delete it?

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Gerber file and Drill file generation

Hello everyone,I'm new to this board layout designing. So plz can anyone help me out in this?I have created a 2-Layer board and also completed almost everything with placement and routing along with...

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Trouble Placing Parts in PCB Editor

I am having difficulty placing a particular part in PCB editor.  The footprint and padstacks are good.  In manual placement mode, I even see the part displayed.  However, when I click on the board to...

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Display properties cannot be edited if Property Editor is invoked from...

Display properties cannot be edited if Property Editor is invoked from Project Manager. Please do it from schematic editor.Why not? Any guesses?

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Integrating EMC prediction features in PCB CAD tools

Dear PCB designers,It has been recently demonstrated that the radiated electromagnetic immunity of a PCB with components could be predicted without resort to complex 3D modeling and simulation tools.As...

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Symbol REFDES on Top Silk and Bottom Silk

I want to have the symbol refdes on both the top silk and bottom silk.I can't seam to copy the top refdes to the bottom.Can these be done?

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FSK modulator

Hi! I am fairly new to Cadence tools. I currently run the OrCad and PSpice 16.6 Lite.I have an FTDI cable that outputs TTL signal when connected to PC. I would like to use that binary signal to doFSK...

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Why not visualize the signal in divider output by 2?

rode this oscillator and used a frequency divider by 2 to simulate the circuit but did not get the signal in 4013. I would  if possible ,  explain and show the error.  I also wanted to see if you can...

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Edge mounted device double sided footprint

HiI have been trying to create a footprint having custom pad dimensions but have been very unsuccessful and a bit frustrated. I need to create a footprint for an edge-mounted micro USB device which...

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How to check break wires in DRC?

Hi, I found some break wires in schematics by visually check. Neither the full Electrical DRC and Physical DRC reported this problem, and the netlist is created without warnings and errors.Is there any...

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warning messages of NC Drill

Hi all,When I try to create manufacturer files, including Drill file I see below warnings in log file which I don't know the cause!I want to know if I should ignore them or not?WARNING(SPMHMF-358):...

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Allegro "right-click" disabled.....

When I right-click no options are displayed. I don't know how this happened. How do I get it functioning again?Thanks

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How define own part templates for converting PSpice libraries into Capture...

Hello,I have a PSpice library (*.lib) with a great number of PSpice models. All models have the same structure. They are defined as a subcircuit with two terminals.When I use the PSpice Model Editor to...

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Capture tcl script to add/modify properties on all parts

I am a complete beginner on tcl scripts.  I have searched and failed to find any info on how to parse through a complete design and add a custom property onto all of the parts in a design.  The closest...

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How to clear session log in capture?

Hi !How could I clear the information in "Session Log " window? Thanks!

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Create layout directly in Allegro PCB SI

Hello, Is it possible to create layout directly in Allegro PCB (without having a deal with schematic):create list of netscreate geometry objectsassociate these objects with netscreate stackupassociate...

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Import Logo

Looking for information to add a company logo to an existing Schematic for a customer and use the output as a template.

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Generate X-Y Centroid data

Hi all,Is there possible if I want make X-Y Centroid data by Allegro 16.6 tool?And how?Thanks all your idea!

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Gerber output problem

I've modified an existing design in OrCad 16.0 and run the post processor.  The Gerber preview looks fine.  But when I view the files in DFM, the bottom layer has no pads and the traces are only a...

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CMOS ROM Troubleshooting

Hello,I am new to the forum and new to Cadence as well. I have designed  both a CMOS and BJT ROM and am trying to perform Gate level simulations with Cadence Allegro. My BJT ROM outputs show correct...

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