community.cadence.com/.../pcbboard.zip
hi guys, I am new to Cadence and PCB manufacturing, I designed a digital clock and did a 4 layer pcb for it. When I run DRC it shows some kind of error with shapes in my thru pins. I don't know how to fix this, I have attached the board with this post. I have 4 layers but components are only in top layer. middle layers are VCC and GND. I gave this to a few manufacturing companies to check and they said it had no issues but allegro PCB is still showing errors. can you guys take a look?
EDIT: This is the error I get it: error message It has some design constraint error. how to fix?
Any help is greatly appreciated