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Allegro PCB designer: possible to export .brd to .mcm (Allegro Package...
Hi! Is it possible to export a PCB Designer (.brd) to Package Designer format (.mcm)? (or, equivalently, to import a .brd in Package Designer?)We have a a 4-layer fan-out board for a flip-chip done in...
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Allegro 17.2: Logo Creation
Hi Team,I am trying to create the company logo by importing the .bmp file via File-->import-->Logo. (Mechanical Symbol: Board Geometry-->Silk Screen Top)But in this method of import the logo...
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Orcad Capture crashes
Hello. Starting from hotfix 050 (rare crashes) to hotfix 052 (often) capture crashes while loading projects with pspice templates. If i delete these templates from HDD everything is ok. And when i...
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Allegro Project Manager
Dear All,Our team has develop the PCB design in Version 16.6. I have install the cadence 17.2. When i want to open the Project files(.cpm files) in this version in the Project manager, i got Error,...
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Altium to Allegro PCB Editor 16.6-2015 Translator error
I am unable import Altium ASCII schematics without an error.I run "trl altium2hdl advanced" from the command line and select "Allegro Performance" license.The "Load Altium" step works, it's the...
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color -toggle display problem
Greetings - I have several ".color" files I use to quickly change views in Allegro. When I go to the "view" pull down in the visibility tab I can select them and toggle class/sub-classes on and off...
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Package keepout to placebound top-DRC
which property can be used to avoid package keepout top to Placebound Top DRC
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Use Filename as Prefix During Gerber Generation?
When generating Gerbers, is there a way to set the "Prefix" cell (or Suffix, for that matter) to the board's filename? This way it will automatically update as revision numbers change, and doesn't have...
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spreading clines
hello.i want to spread clines with equal spacing. i do know how to spread clines between vias.but i am just wondering if i could spread clines between the two end clines.for instance, there are 4...
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assigning net to clines
helloi accidentally deassigned a net on a cline which is connected to a via and a pin.how can i assign the original net back to the cline whose net was remved?
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radius change on dynamic shape arc
helloIs there any way that i can change the radius of the arc on dynamic shapes?If so, can you tell me how?
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Setting DC impedance for nets
We do quite a lot of designs where we use the trace resistance to balance diodes in parallel for DC currents. Is there any way we can set the a impedance constraint for this so we can control the...
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Virus software deleting down load when finished
Our virus software is deleting our down loads right after it finishes. We get this messagePUA 'Generic ML PUA' detected on Hotfix_SPB17.20.050_wint_1of1 https://community.sophos.com/kb/en-us/128136I...
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Simulation Issue
Hi It is my first time using Pspice simulation and I encountered some issues. Could anyone help me to take a look if there is anything I didn't config correctly in the spice model?Thx.** Creating...
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In allegro17.2 HF052,After opening the automatic teardrop, moving the via...
In allegro17.2 HF052,After opening the automatic teardrop, moving the via around the teardrop will run around
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Highlight all Untested nets simultaneously?
Hi All, Does anyone have a method to highlight all Untested nets simultaneously? I’ve generated automatic testpoints. Now I simply want to see a board view (zoom fit) of the remaining untested nets. I...
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Changing the Design Footprint Symbol
Hello,I was wondering if it is possible to move the specified path for PCB Footprint symbol. I have selected the default during the installation. Was wondering if its possible to specify to a different...
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saving a file
helloi started to working on a design file which was worked by a different person.whenever i try to save a file, it says, "performing a partial design check before saving."where can i find a setup for...
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PCB shapes issue
community.cadence.com/.../pcbboard.ziphi guys, I am new to Cadence and PCB manufacturing, I designed a digital clock and did a 4 layer pcb for it. When I run DRC it shows some kind of error with shapes...
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