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Graphics Cards and High-Speed/Miniaturization Options

I just recently started using the High-Speed/Miniaturization options with Allegro 172, and suddenly I'm experiencing crashing at least 2-3 times a day. The error message says "Program has encountered a...

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Allegro 17.2 Desgin Entry HDL Error (SPCOCD-553)

Dear All,I am newbies in the Cadence Allegro Design Software.I am facing the error in the Allegro Design Entry HDL opening. Please find the attached Error for the reference. The Software gets hang...

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select entire net refresh in 17.2HF052 capture is very slow

Hi guy!       I found that select entire net refresh in 17.2 capture is very slow, and there will be similar unresponsiveness in the middle. This problem mainly occurs when selecting GND or VCC....

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[Capture CIS] Preview 3D model for database parts + more component details

HelloUnder Place Database Part in Capture CIS, Is there any way we can get a 3D preview of those parts which has a step attached to their footprint?If not, is there any way to get a more detailed...

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OrCad PCB Editor File Extensions - a definitive list *please*

In the process of creating footprints, board layouts, format symbols and the like, OrCAD PCB editor creates a plethora of files and some sub-folders.We have a repository and want to save out ONLY the...

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Creating paste stencil with both sides in one stencil

HiSo I have a bit of a weird question; I'm trying to create a single stencil with both sides of my PCB on it (this is because my stencil manual printer basically has a minimum size and my board is...

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converting a text into a polyline on dxf export

hellois there any way i can convert a text to a polyline when exporting a design file as a dxf file?

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Bend operations disabled due to licensing and/or DLL installation issues

Hello All,After the installation of the latest Hotfix_SPB17.20.053_wint_1of1, I get an error message in 3D canvas:Bend operations are disabled due to licensing and/or DLL installation issuesIs there a...

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Advice on moving forward. (I believe unit's of measurements caused an issue)

I've posted about this a few weeks back, but work has been hectic, and I haven't had a chance to work with ORCAD since.     Here is what's going on.   I have two boards that have  30 pin connectors,...

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Creating an alternate sch symbol for a multi piece component allegro HDL 17.2

We have a part number, SEAF-40-06.5-S-10-1-A-K-TR  in our system.  It is a connector and has 4 parts (that are listed as variants) to it.   The way it was laid out pin wise was bad. However its already...

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DRC ERROR

Hi everybody, I'm writing because I would like ask to you a suggestion about DRC.For examle: I have a net ( It is a shunt) with an min line width of 1 mm. I need to read the current so I have to take...

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Refresh Capture.ini without restarting Capture?

I have this in my CDS_SITE Capture.ini[Part Library Directories] Dir0=C:\Cadence\Library\LogicThis will load all the OLB libraries within Dir0 when Capture opens. Is it possible to reload it if a...

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Differences between a netclass and a netgroup

Hi ,I am trying to figure out the differences between a netclass and netgroup in constraint manager. Can anyone explain when you would use one or the other ?

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failure of creating net list

Hello, i just started PCB designing in cadence 16.5, ORCAD capture. I draw the schematic in capture and i created my own footprint for package and uploaded the footprint in property, define the pins in...

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square shaped void with radius

hellohow can i change a square shaped void on a shape to a void with a radius at 4 corner?

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copying a void to a shape on another layer

hellohow can i copy a void on a shape on Layer 1 to a shape on Layer 2?

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offsetting a void shape

hellohow can i offset a void shape?for instance, i want to make a 40um square shaped void a 30um square shaped void.

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Thur Pin and Via clearance to shape/plane disappear

Hello all together,I'm staring to learn Cadence (capture CIS and PCB Editor) and at moment I'm lost with a strange problem I couldn't figure out by myself - even after extensive web research and...

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why line to SMD Pin same net spacing DRC?they are one the same net.

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Testprep Automatic - allow pin escape insertion function - doesn't work as...

Hi all!I'm trying to add as much testpoints as I can on a board that has ~380 nets. In the ideal world, I'd like all my testpoints to be located on the bottom layer. In order to accomplish this, I'm...

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