Hi all!
I'm trying to add as much testpoints as I can on a board that has ~380 nets. In the ideal world, I'd like all my testpoints to be located on the bottom layer. In order to accomplish this, I'm trying to use the "Testpret Automatic" support from OrCAD PCB (I'm using OrCAD PCB Designer Professional v16.6 S069), after having set my testpoint to component location constraint in the constraints manager modes.
I have set the parameters (Testprep Parameters dialog) to have the test points on Via pin type only; SMD/Blind; Bottom layer and Single mode; no test grid restriction (0, 0); I haven't checked the "Disable cline bubbling". On the Padstack Selection I have selected a valid "SMT Testpad", which has a pad on the bottom layer only in the padstack and selected a "Thru Via" which I use (among others) in the design. I have also one probe type enabled, with which I want to have a minimum clearance of 2.0mm between the test points.
In the Testprep Automatic dialog, I check "Allow test directly on trace" and "Allow pin escape insertion" and set the maximum via displacement to be 3.0mm. When I run the "Generate testpoints", I get around 120 test points generated, but not according to my expectation. The test pads (vias) that I get are put on one of the three positions:
1. Ether on a track (in the middle);
2. Close to a pre-existing via, and connected to it with an autoplaced cline - the same type as selected in the "Thru Via" field in the Parameters dialog
3. Close to a pre-existing via, and connected to it with a cline, but the via is some other one that I use in the design.
According to the documentation, regarding the Allow pin escape insertion:
"In conjunction with the Thru via field on the Padstack Selections tab and theVia displacement fields, automatically adds an SMT test pad and a via to a net if no suitable test site exists. Use this option for in-circuit tests to ensure top- or bottom-side access to all surface-mount-technology devices or for routed nets without through-hole vias. Routing is added despite the presence of a NO_PROBE area that may be placed over pins. The actual via is placed outside the NO_PROBE area. When locating a via outside a NO_PROBE area, the Via displacement: Max parameter setting controls the distance allowed from the pin to go beyond any NO_PROBE area. Allowing pin escape insertion requires a route keepin."
I expect to get an extra via connecting a trace on the Top layer, to a testpin on the bottom side. I don't get this, and just have all the connections made to pre-existing vias on the board.
I have played around with different grid sizes on the Etch layers, as well as different displacement Min/Max values for the testprep vias - I still didn't get new vias connecting the top layer nets to the bottom one, so that a test via can be added. I read on couple of threads here that dynamic shapes can sometimes interfere with the pin escape insertion function - so I removed all the dynamic shapes (saved them to a sub drawing for later to be imported back), and re-run the automatic testprep, with the same parameters as stated above - again no new vias were added, and only connections to existing vias are made.
Have I miss interpreted the documentation (if so, please correct me), or am I doing something wrong with setting the parameters?
Please find the pictures of all the setup dialogs on the following link: https://imgur.com/a/T7QtYU1
Thanks a lot for any assistance!
Cheers,
Aleks