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what is making the suffix number of the name of the wire?
the left is a offpageconnector translated from DxD.what i wanted is just: COMBINED_PGOOD_LS, not COMBINED_PGOOD_LS_116296but i am not able to do that. pls tell me how. thank you.
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Can't delete duplicate properties
Inherited a symbol from a vendor library.There are two "Value" properties on the part. (Yes, the property name is Value)One of these has a string assigned to it which is visible. The other is empty. I...
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Do you need purchase high-quality PCB?
Dear all We are one of leading manufacturer of urgent order in south of china,who offer one-stop solution for customer, specializes in providing worldwide clients with high-quality printed circuit...
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CRefer in Allegro System Architect
I am trying to run a CRefer in Allegro System Architect (ASA).Everytime I receive an error message 'ERROR(50) Compilation errors Fatal error(s) found while compiling Please correct the design and rerun...
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How about 8L ELIC HDI?
*Email: Walker.wang@fastturnpcbs.com*Skype: Walker（fastturnpcb）*Website:www.fastturnpcbs.com
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Design Entry HDL 16.6
We had a situation were a design engineer depopulated an IC on an assembly which resulted in having an open input on another IC. Long story short this caused a failure. Now the managers want to know...
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Setting up Constraint Manager to detect unwanted stubs
Hello,My PCB Design had two floating vias and traces. This error was not detected in a DRC check, but with a netlist check from the ab house.How can I set up the CM so that the DRC check will catch...
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Orcad 16.6 TCL: class DboAnnotateRange
I'm trying to automate putting ref des ranges into a schematic (and checking the 'refdes control' box)the tcl doc has the class class DboAnnotateRange with get/set index, but there are no examples, and...
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Creating Rigid Flex PCB
I need to create a rigid-flex design.A question I have is regarding the coverlay, coverlay clearance and stiffener.Do I need to create a coverlay shape, basically the length and width of my flex...
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Altium Import into Cadence
I have a coworker who did a design in altium and it looks like there is in import menu in Cadence import->Translator->Altium PCB in Cadence OrCad. I checked Allegro with 2 different licenses and...
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Manufacturing Menu option is missing
Hi All,I am relatively new to PCB design. But I soon came to learn that in order to obtain the manufacturing files, there should be an option available on the top besides tools and export that aids in...
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Mechanical Hole to Dynamic Shape Spacing
I have a copper pour(dynamic shape) around a non plate through mechanical hole that is always 20mils regardless of the Hole to Shape setting in the constraint manager. There is a property in the hole...
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Constraints in the schematic (DEHDL)
Hi,I'm using Cadence v17.2, Allegro Design Entry HDL for schematics and layout. At the moment, we have constraints at the schematic level (from an old design), and newer constraints in the layout.Is...
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OrCAD Capture Part reference
Hi I am working on a hierarchical Schematics and almost done with it. Before transferring it to board layout, i have to add some small parts here and there on the schematics. The issue i am...
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Artwork title blocks
I'm using 17.2I'm looking at an older design where each of the film views have a DRAWING FORMAT/FILM_BLOCK that enables the artwork film control info (film name, mirrored, positive/neg) info to be...
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Artwork for bottom layers
I'm using 17.2I would like to show the bottom layer assembly and silk view with just the board mirrored but not the title block. How do i do this? The 'Film mirrored' checkbox under the artwork...
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adding a via
HelloI am trrying to add a via by using "Define B/B Via" on PCB Editor.After I select a via and put it on "Padstack to Copy", select Start Layer and End Layer and press OK button, it says "Enter a name...
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copying shapes and clines from another file
I am trying to copy shapes and clines from another file by exporting and importing sub-drawing but after 90 percent completed, it freezes or takes a long time to complete.Did I do something wrong?
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purging unused symbols
how can i purge all unused symbols?i deleted all unused symbols but they are still showing on the netists.i have also purged all unused nets by typing "purge unused nets" but the constraint manager is...
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