Hello everyone.
I have been working on a project and I've come across such issue.
I created a schematic of a power converter. Here's a piece of it. Q1 transistor is in SOIC-8 package (1,2,3 - Source, 4 - Gate, 5-8 Drain).
I assigned footprints and when I imported netlist, I noticed that there are no logical connections between pins (Net number is correct, however). How can that problem be solved?
