Is there a setting for automatically naming nets from port names in a hierarchical design? That is, when creating a netlist for Allegro in Capture.
↧
Channel:
Cadence PCB Design Forum
X
Are you the publisher?
Claim or
contact us
about this channel.
X
0
Channel Details:
- Title: Cadence PCB Design Forum
- Channel Number: 3711444
- Language: English
- Registered On: July 11, 2012, 9:59 pm
- Number of Articles: 5525
- Latest Snapshot: December 26, 2021, 11:21 am
- RSS URL: http://feeds.feedburner.com/cadence/community/forums/27
- Publisher: https://community.cadence.com/cadence_technology_forums/f/pcb-design
- Description: From schematic to autorouting what are your challenges in producing high-speed designs?
- Catalog: //kittenhood4.rssing.com/catalog.php?indx=3711444
© 2025 //www.rssing.com