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Issue with step file export
HelloTool version :17.2-2016 S063When I export step file ,outer layer (Coverlay) thickness is not added to step file (Refer first image) .Showing wrong PCB thickness (0.28mm) on stepfile.As a...
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Is it normal that allegro 16.6 "add connect" action doesn't allow drawing...
I'm trying to draw tracks from one net pad to other pad/via of the same net (they are connected electrically = rastnets). But when adding connect action, I'm unable of tracing the track making a...
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DRC flag Red after creating VCC shape plane
I’m learning with Allegro PCB Designer tutorial. Creating a Shape for the VCC Power Layer, isn’t working as stated. Prior to the operation the DRC flag is Green. Yet, as soon as I complete the...
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DRC Problem after updating trace width - now won't go away
I have an interesting problem. I have eight (8) connectors on a PCB. One, for some reason, is giving me problems. I am getting a DRC problem. I have NO IDEA why I am getting this problem. Here is...
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How to rename the layer name in PCB Editor?
Hello all,How can I can edit or change the following layer name?I am self learner of PCB editor. I was trying to design the copy of a file I already have (A reference board file). The above picture is...
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How to convert a pin to only drill/hole for connector clamping in an updated...
I have this symbol in a library project that has been created some years ago.Today I was translating the project to 16.6 starting by updating libs. Then I created the netlist and this process was OK,...
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What is SPIF stand for ?
I am currently going through the Allegro PCB Editor Training Manual. Lab 10-4 mention the SPIF interface. In the PCB Editor Help the SPIF command appears. Though I can clearly understand what the SPIF...
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GND and VCC planes not assigned to GND VCC Nets
Schematic NETLIST is generated without any error. I can Import into PCB Editor from Import > Logic with no error. On my Schematic I have a GND Net and a VCC Net as well as many other Nets. The Cross...
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allegro schematic Hierarchy
Hello, I need to ask a question regarding hierarchy in allegro schematic. I have created one but now i need to make changes to one section so that its not reflected into the other?
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Capture - Net name from port name
Is there a setting for automatically naming nets from port names in a hierarchical design? That is, when creating a netlist for Allegro in Capture.
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Production files generation
I have a question regarding the production files of a PCB. I have added two cutouts on my PCB.When I generate my drill file these do not appear, only the holes of the tracks and the insert components...
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Why the Autorouter use Via to connect GND and VCC pins to Shape Plane
Here are two screen capture of Before and After Autorouting my board. Padstacks have all been revised and corrected. The Capture Schematic is correct. All Footprints have been verified after Padstack...
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Multiple parts for single reference designator
Variants seem to be defined as present or not present.Is there a variant that can assign different parts to the same reference designator? i.e. R17 can be either 0 ohm 0805 jumper or 12k ohms 0805...
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Capture Constraint Man anger
Is anyone else using Constraint Manager within Capture? This is my first time using it. I'm finding that it is occasionally changing some of my constraint values in Allegro. It seems random.
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Strange Dot on final Footprint ?
Picture 1 show a Shape created in Allegro PCB Editor 16.6, file LTshape.ssm The Shape Origin is dead center of the outline 565X400 mils. This Shape is utilized in the PadStack Editor to create...
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Placement by Schematic Page Problem (Not Displaying All Page)
I am using PCB Editor v17.2-2016.I tried to do placement by schematic page but not all pages are displayed.Earlier, I successfully do the placement by schematic pages and it was showing all the pages....
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Easy way to add "charging pads" to PCB/Case Assembly
Hi everyone! I'm working on a small battery powered PCB which will fit inside a small plastic "hockey puck" container. A number of these "pucks" will be sold together with a "charging doc" which will...
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Error: CMFBC-1 The schematic and the layout constraints were not synchronized
Hi, I am in the middle of a design and had no problem going back and forth between schematics and layout. Now I am getting the error message below. I am using Cadence 17.2.ERROR: Layout database has...
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Why a new Package update generate DRC error after waiving ?
I've redesigned a custom TO220FLAT PackageFirst I created a TO220shape.ssm with PCB Editor. Then I created a surface mount T220build.pad in Padstack Editor using TO220shape.ssm. Then I created a...
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