We have an ECSet that has been defined in SigXplorer, imported into Allegro and applied to a netgroup. Five of the six members of the group work as expected and the ICs in the chain map by tag. The sixth does not, and shows this warning:
*WARNING: Xnet pin PCB-0419-X00_16JULY21-TB1 U30.F3 contains mapping tag BL0 but the pin wasn't mapped by this tag.
*WARNING: Xnet pin PCB-0419-X00_16JULY21-TB1 U31.F3 contains mapping tag BL2 but the pin wasn't mapped by this tag.
*WARNING: Xnet pin PCB-0419-X00_16JULY21-TB1 U33.F3 contains mapping tag BL3 but the pin wasn't mapped by this tag.
*WARNING: ECset pin pcb-0414-x00__-__copy U30.M9 contains mapping tag BL0 but the pin wasn't mapped by this tag.
*WARNING: ECset pin pcb-0414-x00__-__copy U31.M9 contains mapping tag BL2 but the pin wasn't mapped by this tag.
*WARNING: ECset pin pcb-0414-x00__-__copy U33.M9 contains mapping tag BL3 but the pin wasn't mapped by this tag.
*WARNING: 3 Xnet and 3 ECset pins with unmatched mapping tags found.
Net Schedule: Template Defined
PCB-0419-X00_16JULY21-TB1 R194.1->PCB-0419-X00_16JULY21-TB1 R87.1
PCB-0419-X00_16JULY21-TB1 R193.1->PCB-0419-X00_16JULY21-TB1 R194.1
PCB-0419-X00_16JULY21-TB1 R89.1->PCB-0419-X00_16JULY21-TB1 R86.1
PCB-0419-X00_16JULY21-TB1 U21.B44->PCB-0419-X00_16JULY21-TB1 R89.1
PCB-0419-X00_16JULY21-TB1 R86.1->PCB-0419-X00_16JULY21-TB1 R193.1
PCB-0419-X00_16JULY21-TB1 R193.2->PCB-0419-X00_16JULY21-TB1 U31.F3
PCB-0419-X00_16JULY21-TB1 R194.2->PCB-0419-X00_16JULY21-TB1 U33.F3
PCB-0419-X00_16JULY21-TB1 R86.2->PCB-0419-X00_16JULY21-TB1 U32.F3
PCB-0419-X00_16JULY21-TB1 R89.2->PCB-0419-X00_16JULY21-TB1 U30.F3
How do we enforce the correct mapping? It keeps reverting back to the incorrect mapping.
I've contacted our support channel, but wanted to see if any users had run into this before.
Thanks for any feedback you may provide.