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High Pin Count Non-Symetric Land Pattern Creation
Hello, I am new to Cadence Allegro and will need to create a few land patterns that will have between 700 to 1000 pins. I recently created a 220 pin pattern by manually entering pad stack...
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Via's connecting the wrong layers
Hello, Im running OrCad PCB Designer with Pspice version 16.3 Im making a circuit that runs lots of current through it and they need to be connected on both layers. My plan was to do this making lots...
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PTF File
Hi! How can I have one master PTF file? When I create parts in Part Developer, each part has its own PTF file. How can I have 1 PTF file for all parts? How should I link this master PTF file to the...
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WARNING(ORCAP-36006): Part Name....
I get warnings like this all of the time...#5 WARNING(ORCAP-36006): Part Name "C0805_Y5V_10UF_16V_C_3216_ACASE_10UF" is renamed to "C0805_Y5V_10UF_16V_C_3216_ACASE"....sometimes dozens per design. I...
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Flipdesign
Hi All,I'm running both 16.3 and 16.5. My problem is that the design doesn't flip when I click on the flipdesign icon. It used to work, but somewhere along the line it stopped........maybe when I...
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Steps for Back Annotating Resequenced Refdes to CIS
Has been a while since I last went through this process and can't seem to get the resequenced designations back into the schematic.What are the steps to properly back annotate information from Allegro...
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Design Entry CIS to Design Entry HDL
Hi! Is it possible to convert all symbols created in CIS into HDL? How?Thanks.
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Minimum apect ratio for fabrication
Dear all,Can any one tell what is the minimum aspect ratio required for PCB fabrication? Regards,Venkatesh.
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.brd to .step
Hello All,I got a pcb design from cadence to simulate in a FEM solver but i cannot import has it accepts only STEP and .IGES format or COsMOS,So is its possible to store the design in these formats.or...
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Capture complains design is opened read only when it is not
Hello everybody, For some weird reason, OrCAD Capture complains that the design file is opened read only, even when it is not. If I right-click the .dsn file in explorer, and click properties, the...
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Cadence 16.3 and 16.5
Does anyone run both 16.3 and 16.5 on the same terminal? I would like to have both verions running but I am worried about the licensing. If you have any experience with this I would greatly...
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Auto-response
I am travelling till 03-08-12 and will have limited access to emails and phone. Expect a delayed response.
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Issue with netlisting to PCB Editor
Hi all, I am trying to generate a netlist from my schematic to generate the layout for PCB Editor but keep encountering an error which I'm struggling to understand. After generating the netlist, the...
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Adding a new menu item to Allegro PCB Editor
I want to add, or really append, a new menu item to the Allgro PCB Editor menu. What is the easiest way to handle this without having to modify the installed menu? Maybe someone has an example that...
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Cadence HDL symbol wizard pin spacing/length?
New to Cadence HDL DE. With the symbol wizard, I'm getting pins that are .200" long and .200" centers (compared to other symbols in library that are .100" & .100"). Any suggestions what to check?My...
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shorten (edit) ref des silk after hierarchical layout is complete, Allegro 16.5
I have three layers of hierarchy in my design and the ref des silk gets very long after the reuse symbols get packaged, i.e. R412 becomes R412_0 (and even longer for some components). After I place...
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Can you save a part symbol from a PCB design into the library?
I've successfully translated a PADS layout into Allegro, but it didn't create a .dra file. Is there a way to select that part symbol on the database and save it so I can update the dra file?
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SLPS Option error
Hi, Whenever I open Matlab and setpath add all the slps library files and save it after doing this I get few sample circuits by doing 'slpslib' then if I simulate any circuit I can't able to simulate...
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Component Place Bound DRC not working...
Hello, Somehow I have managed to disable the component place bound DRC and I have been unable to find out where to enable it. Can any one point me to the correct location? Any help would be...
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Line to Pad Spacing DRC .050mm / .050mm Design
Hello, I am working on an very dense design using .4mm pitch BGA's with .250mm pads. In order to escape the part within the desired layers we have decided to reduce the min line width and spacing...
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