Quantcast
Channel: Cadence PCB Design Forum
Browsing all 5525 articles
Browse latest View live

Image may be NSFW.
Clik here to view.

Use of "time" as argument

In a very simple circuit I am not able to use "time" as an argument inside a Resistor value, nor Voltage source.In fact, what I need is to simulate a frequency chirp up signal using transient...

View Article


Image may be NSFW.
Clik here to view.

Regarding Analog Switch Operation under Analog Lib in ORCAD Capture

Hello I would like to use switch under Analog Lib but i am not able to get expected output. Can some one please tell the exact operation of switch. The output across should be vary between 24 to 0V but...

View Article


Image may be NSFW.
Clik here to view.

Editing time option in allegro- How to use that

Hi all,I m using allegro 16.5 version. I want to know the details regarding the editing time option in status menu of allegro layout. Give your valuable suggestions.Thanks

View Article

Image may be NSFW.
Clik here to view.

soldermask increase in allegro

Hi,Is there any option to increase the soldermask of pads automatically by 2 or 3 mils globally with respect to pad in allegro?Rgds,Shilpa

View Article

Image may be NSFW.
Clik here to view.

Can we increase the soldermask size globally for all the components in...

Can we increase the solder mask size globally for all the components in Cadence Allegro.Is there any option to do so. Thanks in Advance.

View Article


Image may be NSFW.
Clik here to view.

Changing Artwork Name

I have been trying to change my artwork layer names. The manual shows the following but that does not work. Any ideas ?Film Name: Displays the name of the film record to be edited. You cannot edit this...

View Article

Image may be NSFW.
Clik here to view.

same net via spacing

Is it possible to set a maximum via to via overlap allowed? I have a bunch of vias that are used in thermal tabs and some of the via pads are overlapping. I don't want shut the DRCs off because I would...

View Article

Image may be NSFW.
Clik here to view.

Modify thermal relief on single pin

Hello all,I have a pretty simple problem that I can't get the right search terms to be able to google. I need to delete one of the connections on thermal relief but I can't seem to do it.  To clarify,...

View Article


Image may be NSFW.
Clik here to view.

rotate vs spin

Why do the menus sometimes show "spin", and sometimes "rotate". Not the same?

View Article


Image may be NSFW.
Clik here to view.

Connecting SMD pin pad to GND copper plane

Hi,I have all the components placed and routed on the board. Now for mechanical mounting purpose I have two SMD pin pad on the bottom layer(its 2 layer board). Now I'm supposed to connect this pin to...

View Article

Image may be NSFW.
Clik here to view.

How to set up via hole to via hole constraint in Allegro version 16.3?

I mostly use Allegro version 16.3 to support customers.I can set component hole to hole spacing in constraint manager.However, this does not flag via hole to via hole errors. Is there a way to set up...

View Article

Image may be NSFW.
Clik here to view.

xsection and design parameters not working in PCB Designer

We have updated to 16.6  I am having a problem with cross sections and design parameters.  Setup>cross-section or Setup>design parameter do not pull up the expected screens.  In fact they pull up...

View Article

Image may be NSFW.
Clik here to view.

OrCAD Does not release libraries until you close the application

There are multiple users of OrCAD on my site and we are experiencing an issue where if someone opens a library, when they close it no one else is able to open the library. This is only resolved if the...

View Article


Image may be NSFW.
Clik here to view.

Free PCB Penalization software

Hi,Just like all other people, i'm also wondering why would cadence doesnt provide software for making pcb panels. After going through various post without finding any proper solution, I'm asking all...

View Article

Image may be NSFW.
Clik here to view.

DRC not flagging line to hole clearance violation

Hello Cadence Community,I have a weird problem.  I have a board with two mechanical symbols, each with an unplated mechanical pin padstack.  If I route a line through one hole, I get a DRC error while...

View Article


Image may be NSFW.
Clik here to view.

Place Part Library listbox

Is it possible to make this listbox larger? What a pain!

View Article

Image may be NSFW.
Clik here to view.

SI analysis using ORCAD 2015

Hi all,As of new feature of ORCAD 2015 release, we can do SI analysis in ORCAD tool. I wanted to know, how effective it is? Is the simulation level similar to Hyperlynx?And how can we do SI analysis...

View Article


Image may be NSFW.
Clik here to view.

Arduino Shield OrCAD

Hello everyone,I am a newb to OrCAD. I was wondering if anyone had or knew where I can find an Arduino Shield footprints for OrCAD. After hours and hours of searching I can only find footprints in...

View Article

Image may be NSFW.
Clik here to view.

Hierarchical Schematic not printing all pages

I'm using Orcad 16.5 and have modified an existing (ancient) schematic that had 80 pages.When I choose "print" from the schematic level, the output only contains one of each of the unique pages and...

View Article

Image may be NSFW.
Clik here to view.

upgrade projects from Orcad 9.2 to Orcad 16.6

Frankly, I am new to PCB layout and ORCAD as well. I would appreciate it very much if anyone would give me some input on this.I have PCB layout projects and schematics designed in ORCAD 9.2. Now I...

View Article
Browsing all 5525 articles
Browse latest View live


<script src="https://jsc.adskeeper.com/r/s/rssing.com.1596347.js" async> </script>