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Cross talk for parallel nets in different layers
Hi,I want to know how can we perform cross talk analysis if i have one net running in 1st layer and the other net in the 2nd signal layer which are parallel to each other. how can we do this in Sig...
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SI Design analysis
I am trying to do the SI analysis of the simple circuit, I was able to calculate the impedance of the microstrip lines but i need do the overall impedance calculation of the design & how it should...
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Differential Pair Routing
Hello,Is it possible to route two or more differential pair at same time??Suggest if possible...
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how to copy right PART reference in multiple board design in 16.3
Hi sirI put 5 pcs same PCB design in one panel.I try to copy the first finished layout to another 4 pcs but the part reference come to R* or C* while they should be R1 or C1.It should be complete COPY...
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What are these white triangles on the symbol?
Hi, does anyone know what are these white triangles on the pins, and how to get rid of them? Thanks in advance.
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Allegro - Stuck with red DRC status, nothing in DRC Report
My DRC status is still red, indicating a DRC error: But when I run Tools > Update DRC, then Tools > Quick Reports > Design Rules Check (DRC) Report nothing shows up in the window. Same with...
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How to find Cadence install location in 17.2?
SPB 17.2 has removed the CDSROOT env var, which I'd used to determine the installation folder. I used it in a post-install script which configured users' PCs.Is there a way to determine the install...
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cdsMsgServer.exe - entry point not found
Hi,I upgraded to the latest version of Orcad PCB designer - 17.2-2016 S0333 (1/22/2018) windows SPB 64-bit EditionI am getting the following error when I launch the PCB designer. Any idea what to...
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Capture cloud?
Just saw this: https://orcadcloud.ema-eda.com/ema-edaLooks like a scaled down version of Capture's desktop application in the browser. The information seems scarce around this. Anyone know what...
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Fail to export pdf using ghostscript
Hi Im using Orcad 17.2 and the script used for exporting schematic pdf's is Ghost script gswin64c.exe. But Now i'm getting an error while exporting pdf which is,ERROR: undefinedOFFENDING COMMAND:...
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Random numbers after net name
Hi, I am relatively new to ORCAD and I have a schematic which is on multiple pages and I have multiple nets that are having a random number assigned to them on different pages. For example, I have...
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Allegro Design Entry HDL (DEHDL) console window - my desired group is empty...
I've been using the command console and grouping items for many things recently and thought i had a grasp on it, however there is something i ran into that i don't understand. I'll post the commands i...
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how to generate basenet report and Cref in Cadence Concept HDL ??
Hi All,How to generate basenet report and Cref in cadence concept HDL ?? i generated but i got some issue in this file.Kindly help any one for this quries. Spawning... creferhdl.exe -proj...
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Difference between Hyperlynx vs SystemSI about R_pin/L_pin/C_pin in IBIS model
Dear Experts,I had run DDR4 DATA timing with Hyperlynx (DDRx batch in Boardsim) and SystemSI (Cadence Sigrity).The result simulation are so different between two software. I detected the reason of this...
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Spacing betwin shapes
Hi allI'm drawing the power plan. I have a big shape (principal). Inside a this shape I need to draw other shapes more small. For evry shape i want to have different spacing. (shape to shape)....
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PCB Design for Noobs
Hello,I have an original circuit that I've been soldering up on perfboard with a ton of jumper wires and am getting sick of it taking all day to build 'em. I'd like to transfer the schematic over to a...
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Creating a Board outline
I am trying to create a board outline and would also like to know how once I have created the board outline how to bring it in to associate it with the actual design.I would like to draw a rectangle...
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spice model for heterogeneous schematic parts
I tried to associate the pspice model for the heterogeneous IC parts in the orcad schematics but getting the error message as the flow is not for the heterogeneous parts only for homogeneous parts....
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Current carrying Capacity of filled vias
Hi,While discussing with my colleague, he said conductive filling of vias has no impact on current carrying capacity.When current carrying capacity of vias depends on the plating thickness, why via...
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Urgent query about defining oval slot rotation in *.DLT file for custom...
Hello Group,I am having issue in the last stage of my design. In the *.DLT template from Cadence under folder \share\pcb\text\nclegend. Below note is mentioned.; Matching of data to a hole is done on...
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