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Copper area in the footpring and DRC errors
Hello,in my factory a previous colleague has created many footprints like the one in the picture. There is a copper area in the footprint; this area encompasses two pins. In this way the area must not...
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Reducing pad sizes on a multiway header.
Hi all, I'm using OrCAD 17.2.2016 and I've a connector which has 120 pins and I need to reduce the pad sizes on the default footprint on a 7layer PCB. I did ask this before about a year ago(?!!) but I...
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Find and Replace is horrible (17.2). Is there a way to Find/Replace prefix or...
I’m just trying to do a find/replace to update a bunch of Hierarchical Port prefixes from “Px” to “P0”. I would love to be able to do this for other cases like net names, like where a data bus has a...
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Change default units in Padstack Editor
Hi,Is it possible to change the default units in the Padstack Editor to be something different than mils?Many thanks
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Differential pair parameters calculation
Good day to everyone! I'm using Cadence Allegro PCB Editor 17.2 with high speed license. Is there a way to see which formulas Cadence uses in Transmission line calculator+diffpair calculator in PCB...
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Protect from wire connection on edge of hierarchical blocks
Hi all,I find it hard to detect two pins of an hierarchical block that are connected by a wire link if the wire is placed on the edge of the hierarchical block outline. This has created faulty layouts...
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Connect footprints from PCB Designer into Capture
I have received BRD and OPJ files etc from a freelance designer, when I try to run design sync in capture I get many errors regarding missing footprints. Seems there are several libraries which were...
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Multilayer pad tricks?
So in my quest of learning this software I've been sent a file with a large header. some of the pins require high currents between relatively small pins, I noticed between layers some of the through...
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Double vias for high current tracks in Orcad 17.4 PCB Designer Standard
Hi,We have some thicker 50mil tracks that need higher current capability.I want to 'double up' on vias for these tracks, but OrCad won't allow stitching through the board with both vias. See below:If I...
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A bus of netgroups
Hi, Is it possible to make a bus out of several netgroups in Capture? I have created different netgroups named CH0, CH1, CH2 .. CH19. Can I connect them together as a bus named "CH[0..19]? When I tried...
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Compare 2 Brd
Hi ,I need too compare 2 Brd .I found the command Tools-> Design Compare , but nothing happened . What I'm doing wrong ?I used the 17.2 with the last Hotfix .Thx
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Turn on/off visibility features in the active layer
Hello All,I am new user to cadence and I wanted to know how would write a script to turn on/off cond or via or pin..etc for the active layer using a bindkey?Thanks
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Signal and Pin size doesn't match. Error 150 DEHDL
I'm brand new to cadence. I'm using DE HDL to edit a schematic, and I get Error Code: SPCOCD-150: SIGNAL CONNECTED TO PIN HAS INCORRECT WIDTH.When I went through the DE HDL handbook, it said the...
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How to replace all reference designator properties in OrCAD Capture?
Hi AllIf I want to change all of C to CAP in OrCAD Capture Propertiesif the design have a lot of lists, I can't change one by one is there any way to replace with Ctrl+F matched word feature?regard
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(SPMHGE-670): Impedance Analysis Failed.
Hi all, I have OrCAD PCB Designer Professional 17.4. I need to do Impedance Analysis but I receive (SPONGE-670) error. Could someone help me? Thanks.
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Diffpair impedance calculation
Hi Everyone,I am a new hardware engineer. I am little bit confused while I compare the results from cadence tool and saturn pcb design tool for diffpair impedance matching. why do these two results...
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Warning while placing parts on schematic on existing wires
I apologize if this is not the right forum but I didn't found a forum about schematic capture.I'm recently passed to Orcad 16.2 and I have found an annoying problem while placing parts on schematic: if...
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How to add an external Package Length value to a net length constraint
Hi,I am trying to set up pin pair length constraints in the Relative Prop Delay part of the Constraint Manager but I need to add an external Package Length value to the calculation. There is an...
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ERROR(ORCAP-1530): cannot create directory
why am I seeing this? why is the help file void of anything referencing this?I have tried to link two files I have received from a contractor using design sync, this is the error I receive
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Create a opening in a existing copper pour.
I have created a cavity opening on all of the layer on the 8 layer board I am working on. Now to make changes to this board I need to add 2 more layers. So first I copied the shape from another layer...
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