Group properties for Symbol in Page
Hi,How to make a group properties for a symbol in a page in DEHDL while we take in the pcb edtior page should come ,so easy for placement. Regards,Giriprasad
View ArticleOrcad Capture TCL scripting
Hi All,I would like to use Orcad Capture TCL scripting. Before the 1st hotfix of 16.3 the command window in Capture echoed all of the operations performed during the editing session. Also .captcl...
View ArticleWindows 7 - Allegro Network files slow
I have both an XP box and a windows 7 Box attached to our corporate network. Both have the same releases of the Cadence tools and same Cadence service pack/Hot fix releases (up to date as of...
View Articlefunction key
Hi,Is there a way to combine following commands in a single key using maybe alias or funckey?commands to combine:shape add, right click, assign net.. Regards,
View ArticleLibrary Construction in Allegro and Design Entry HDL
I have used OrCad Capture CIS and Layout before and the library system was fairly easy to follow. But I now need to use Allegro and Design Entry HDL for part creationCan anyone tell me how the library...
View ArticleHow to change the thickness of wire?
How to change the thickness of wire, in PCB Designer? I am using Cadence 16.5, and I know how to change the wire width, just wondering how to change the depth or thickness of the wire~
View ArticleAllegro 3D-Viewer Bottom Component View not correct
When executing the 3D command in Allegro PCB Designer 16.6, the top components are placed correctly with the smt leads flush on the top conductor surface. However, if I rotate the design from within...
View ArticleCreating multiple PDF files in Allegro with Script
Hello all, I am trying to find a way to create multiple PDF files with single script. (Separate files) I would like to select few of the required layers I have setup to be printed through Allegro and...
View Articleallegro to PDF cross probing
Hi,Is there any option to created cross probing from searchable schematic PDF to allegro pcb editor ??Thanks,Shilpa
View ArticleFabmaster does NOT recognize Allegro "virtual" test points
Case Number: Case 45479585Case Reference Number: ref:_00Dd0c1Z9._500d07xDZD:refCase Abstract: We have been using the Allegro TestPrep tool for years to create testpoint data ( Vias ) for our assembly...
View ArticleMulti layer Board design in OrCAD 16.0 Layout.?
Hi, Me was trying to do the multi layer PCB with (Top, Bottom, Gnd, Power). Still i am trying that to find out any tutorial for multilayer board routing technique. can anyone provide me the better...
View ArticleHow to put the Multilayer board in Layout 16
Hi, I had drawn the schematic and trying to put 4 layer board.What should i have to do? Suggestions of the four layer board.
View ArticleHow to setup DRC to allow package overlap?
How to setup DRC to allow packages overlap?I am doing a very compact design, and some packages have to be layout overlap. But the DRC continully tells me an error(I know it will be OK). So my question...
View ArticleHow to connect a via in few GND layers while disconnecting it on remaining...
Hello All,Is there any other way to connect a via(having GND net) on few GND layers and disconnect it from the remaining GND layers. The two ways I know are with limitations as belowTo create route...
View ArticleSectioning in DE HDL
Hi, a newbie 's question. What does sectioning do in DE HDL?So far I only learnt that sectioning a part can display the pin numbers of all the pins of that particular part, and of course a psm must be...
View ArticleChange the via type while routing a 2 layer board in 16.6
I have a 2 layer board defined in my stackup. I have added 3 vias into the Phyical constraint set to make those via choices available for routing.I have also configured my working layers to both top...
View ArticleWhy I have problem with wiring?
I created this pad, inside pad is signal pad, outside is GND, the net wiring is okay but when i do routing of inside signal pin, it displayed : E-[SPMHAC-20]Unsuccessful route:cannot find a path...
View ArticleDifferential pair routing issue
I am new user, have few questions need to get help.Appreciated. Working over time at weekend. :( 1. I attached the two pictures, one project DP routing is the first one, another project is the second...
View ArticleCopper pour shapes: Can I change the net assigned to it?.
Took out a power filter between my main pour and the isolated Vdd patch, but struggling to connect both shapes into one.Is it easier to just delete the disconnected patch?
View ArticleModels missing from PSPICE - OrCAD 16.2
HelloI have a problem. I can't simulate a very simple circuit because the models are missing. I am very new to OrCAD (version 16.2) so I was doing the tutorial on creating a schematic of full adder and...
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