Change host id in license file for cadence 16.5
Hello! I want to install cadence 16.5 software to a different pc and since i have purchased only one license, i have to transfer the license server to the new machine.How can i do it? From what i...
View ArticleQuestion #2: How do I move the pins of a symbol?
At least, I think it's a symbol. It's a rectangle with two pins inside it that I need to move closer together. How can I do this? So far all I can do is move the whole symbol, or delete it. Is the...
View ArticleExport schematic to EPS file
Helloto all,I madetheschematicin Captureand I would like toexport itas an image inEPS format.I useOrcadCapture16.5.Howcan I do?Thank you!
View ArticleNeed help : Custom menu - System Connectivity Manager
Hi all, Aplologies first if this is not the right place for the query.I am planning to call an internal tool from the SCM menu and i am able to call the tool by customizing the "tddCustomizeTBNEW.txt"...
View Articlesave schematic as a model in library for reuse in orcad capture
I want to save my schematic drawn as a part in a library so that I can reuse it in my complex circuits.Please help me out.
View ArticleAdding custom Properties to Part Symbols
Is there a way to add specfic properties to a part symbol, such as "created:", "modified by:", "comment" or other company specific requirements?
View ArticleHow to Lock constraints
Hi ,I wanted to know if its possible to lock constraints in constraint Manager so that once constraints are set it will not be changed knowingly or unknowingly. Thank youRegards Prasanth
View ArticleConverting Existing Vias to BB Vias
Hello all, I am revising a .brd file on Allegro 16.5 that has already been routed throughout 6 layers. All the vias used where Convensional vias with no BB vias. I am trying to convert most of these...
View Articleis it possible to open the constraint in excel ??
Hi everyone,is it possible to open the constraint (like same apperance shown in contraint manager) in Ms-Excel.i want same apperance in my excel also as shown in image file .i am splitting address and...
View Articlehow to remove the pundle nets ??
hi everyone,in contraint manager i set the address 0-14 nets in group .it is create like puldle of nets as shown in below image.how to remove the pundle nets ??wrongly i place the via over the fanout...
View ArticleHow to create Touchpad buttons in Allegro 16.6
Hi, Could anyone tell me how to design Touch pad buttons in cadence allegro 16.6.?I have designed many simple circuits, but i dont know how to design a touch pad. Some Touch pad specific datasheets...
View ArticleHow do I supress my keep out areas in the 3D View? (Version 16.5)
I am trying to export my design to an IDF file format, but I can't suppress the keepout areas in the 3D view. When I try to set the "Default symbol height" in the Design Parameter Editor to 0, it...
View Articlecreate footprints in pcb editor.
how can i create a footprint in pcb editor? i remember in orcad i used the library manager. But i have seen in another post that pcb editor haven't got anything like library manager. is that true?...
View ArticleGround plane help
Hello,I am new to Allegro and I am struggling with creating a ground plane. For example, in the attached image, jumper J18 pin1 (a plated hole) is assigned to the GND net so I was expecting the ground...
View ArticlePAD & footprint help me I am confused
Hi, this is my firs post there,I used altium 3 year but now I need to design high frequency and impedance matching and DDR3 and etc so I changed my plane and I want to use allegro Cadence, but I have...
View ArticleSigNoise Errors/Warnings
Hi,All of the sudden whenever I open Cross-section and try to change Coupling Type or go do do a diff route on this particular board, an error dialog box named "SigNoise Errors/Warnings" pops up which...
View ArticleNET SHORT DRC CHECK IN ALLEGRO16.6
Hi Good day ! I am using allegro 16.6 version If I run Design Rule Net short check report , there is no short in the design , but when I check manually all DRC I found net short DRC having spacing of...
View ArticleCross section not working properly
Hi All, I am not able to add dielectric below bottom layer. But I can able to add above top layer.Can anyone help me please?
View ArticleCadence_tool_Issue
In one of my recent project.i faced some issue with cadence tool. I created a test design to explain the issue in detail.Actual issue is that the net “VCC_LOAD+” is connected to Global power net...
View ArticleLayout to ODB++ Export
Hello,I’m trying to export PCB build data from Orcad Layout 16.2 but the exported ODB++ files are not complete according to the board house.The help file in Orcad Layout points to a link do download...
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