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Convert Schematic from Altium to Cadence

November 13, 2014, 11:50 pm
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Hi All,

I want to convert Schematic files from Altium Designer Summer 2009 (.SchDoc) to :

  • Cadence OrCAD Capture Schematic non-hierarchical EDIF v 9.2 or 10.x or 16.x (.EDF) (.DSN not supported) (pstxref.dat, pstchip.dat & pstxprt.dat files if possible)
  • Cadence OrCAD Capture Schematic hierarchical:  pstxprt.dat, pstchip.dat, and pstxnet.dat (Select top-most level, Create Netlist)
  • Cadence Allegro Layout Board/MCM File version 14.x, 15.x, 16.x (.BRD/.MCM)
  • Cadence Concept HDL Packaged Schematic Files(pstxref.dat, pstchip.dat, pstxprt.dat) (Select top-most level, Export Physical, retrieve files in Packaged folder)

It's possible to convert to at least one of thees formats ?

Best Regards.

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copy and paste parts between 2 separated boards

November 14, 2014, 8:26 pm
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Hi Guys,

I want to copy and paste some parts from reference design board to my design board, just for reference routing. Can I do this and How?

Thanks for all support!

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Copying

November 14, 2014, 9:48 pm
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Yes you can. Use File-> Export-> Subdrawing from the reference design and File-> Import-> Subdrawing to the new design.  Use your find filter and follow the prompts in the command window.

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Another broken forum issue

November 15, 2014, 3:09 pm
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First -- who from Cadence even pays attention to this forum? It seems like no one.  The sorting issue is still not fixed.

Now I see where if you reply to a message without being logged in first, it logs you in and takes you to a new topic post -- this never happened before.  It should take you to the topic you were replying to.

Cadence -- what's up?

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STEP file/ref desig

November 16, 2014, 5:04 pm
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I recently took a PCB Editor STEP file I made and imported it into ProE....then made a 3D pdf out of it. Our customer loved it that they could rotate it...zoom and even take measurements off the pdf. But they asked for the ref designators to be part of the STEP. I'm pretty sure it cant but figured let me ask here. No go right?

TIA!

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After adding a symbol to schematic, adding wires+netnames, how do I display nets? (Using scripting)

November 17, 2014, 12:23 pm
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I have a Concept Design Entry script (schematics) that I have pasted the beginning of below. I notice that when I open this schematic after running this script with nconcepthdl, that the net names are not displayed. When I right-click the symbol and then click the 'section' menu item and then the 'section' sub-menu item... the net names are shown.

Can someone help me achieve the same effect except purely through scripting?

Beginning of script:

write
hier_write
add <page_border>myPageBorder
(4000 -2500)
add myFavSymbol.sym_1
(-25 -950)
wire AJ1 (200 2000) (200 2000)
wire A29 (200 1850) (200 1850)
wire AJ9 (200 1750) (200 1750)
wire AD3 (200 1650) (200 1650)
wire AD1 (200 1600) (200 1600)
wire V27 (200 1700) (200 1700)
section
write
hier_write
section
write
hier_write
_PageInsert 1 2 -noconfirm
add <page_border>myPageBorder
(4000 -2500)
add myFavSymbol.sym_2
(-25 -700)
wire AF2 (200 1500) (200 1500)
wire AJ10 (200 1450) (200 1450)
wire U27 (200 1400) (200 1400)
wire N1 (200 1350) (200 1350)
wire N2 (200 1300) (200 1300)
wire AE3 (200 1250) (200 1250)
wire AE2 (200 1200) (200 1200)
wire H5 (200 1150) (200 1150)
wire AC2 (200 1100) (200 1100)
section
write
hier_write
section
write
hier_write

just before the end of the script file:

write
hier_write -quit

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almost same schematic in Capture

November 17, 2014, 11:55 pm
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Hi, 

I am drawing a schematic with OrCAD Capture, I have several pages are almost the same, e.g. page1-6, the only difference is the net name in page1 is "IC1_xxxx", in page2 will be "IC2_xxxx", etc.

Is there a easy way to create page2-5 based on page1? Can I rename all the nets name in one page?

Thanks

Chris

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Logomaker command error occurs?

November 18, 2014, 3:59 am
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Hi..

I had followed the instructions of  Dave's procedure. When i am try to load command error occurs, i will attach ILINT file,note me that  where i have to insert the command of the 

                                  load("logoMaker_public.il").

I had  Installed potrace-1.9.win32 and ImageMagick-6.7.0-10 ,but it showing in command line as
Command > logomaker
E- *Error* _gets: argument #1 should be an I/O port (type template = "p") - nil
Command >

pls let know details. I don't know what mistake done by me.Any help please.

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Umarked Components.

November 20, 2014, 1:34 am
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How should i ensure, my board have unmarked all components? will i get any report if i unmarked the components in allegro layout file??. because i need that report for DFT test wether all components are unmarked or marked?

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Design Authoring: any plans to update schematic editor?

November 20, 2014, 2:00 am
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Are there any plans to update Design Authoring schematic editor to make it more in-line with modern user interface practices?

E.g option to zoom to the mouse pointer with just a scroll wheel, don't keep component selection after copying etc?

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Grid Spacing in Allegro Design Entry CIS not saving to INI file

November 20, 2014, 7:07 am
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I am trying to have the default Grid Spacing of 1/2 of pin to pin in Allegro Design Entry CIS.  If I go to Preferences and set it, it works fine for the current session, but in the next session, it reverts back to 1/1 of pin to pin.  Is there some syntax I can manually put in the INI file to create the default I want?

Running version 16.6 s038.

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Allegro 16.5: How to display filled pads.

November 20, 2014, 10:42 am
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I need to display filled pads using allegro viewer 16.5. This was simple in 15.7, pull-down menus dot me there quickly.  But 16.5 I have spent a great deal of time looking for this and have not found it yet.

 

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Open Gl Option In Allegro PCB Editor

November 21, 2014, 2:52 am
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What is the significance of this Open GL. What is the use and what happens if it is enabled

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design reuse - ref des renumber - back annotate

November 21, 2014, 5:35 am
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Would like to leverage design reuse primarily for placement and top/bottom layer routing and duplicating one type of circuit (including .mdd) multiple times. I understand that gen_subdesign and use_subdesign along with applying subdesign_suffix at the schematic level will be needed for multiple placements. The problem is that in house tools cannot handle reference designators with _ in them. Any chance that I might be able to renumber the ref des after placement to remove the _ and then back annotate to the blocks ? If so what would I need to do with the packager and/or block properties moving forward to preserve these renumbered ref des?

 

 

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3d views of holes?

November 21, 2014, 3:15 pm
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I can create a 3D view of a part by using the "place_bound_top" info and setting a package height. 

If I just have a hole or a test pad, even if I add placement boundary, there is no right click for properties that includes 'package height'.

How I you do a 3D view for these?

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Silkscreen texts are get moved from certain distance of component?

November 21, 2014, 10:22 pm
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Hi...

For My board ,the silkscreen texts are get moved at the particular distance with component .When i try to move the text over the distance of component , a line with silkscreen refdes text  along get moves for selected component.

The line with the refdes text are also get moved. For the refdes the texts should been get only enabled, but for me line and text are get enabled in the same layer as 1st pin reference of component .I had tried some user preference settings changes, but i cant able to find the solution for this option.

Recently we had updated the software hotfix from 16.6_S027 to 16.6_S038. Might be something had happened during the updation. 

Any solution for this problem.

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Spacing Error

November 22, 2014, 8:40 am
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Hello,

I have a problem with Orcad PCB. I'm not very expert and I don't know how to solve this problem.
In a board I have a LCD display that will be mounted with metallic spacer so in the real board there will be some components under the display (between the display and the PCB).
Obviously Orcad PCB doesn't know this and I get "spacing error" when I run DRC because the LCD is overlapped with other components in the layout project. It's is placed on the top layer like other components that will be under the LCD in the real board.
How can I exclude the LCD from the spacing error check? I don't want to disable the spacing error detection for every components but only for the display LCD.
Is it possible?

Best regards.

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Convert Orcad Capture to Design Entry HDL

November 23, 2014, 7:41 pm
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It is so disappointing that we dont have Cadence supported Translator with in our own Cadence tools, I would like to translate Orcad capture schematic to DEHDL flow, I used cap2cond.exe to do the same, still this is not working and stopped in middle. It is not actually creating pc.db, and this method is not supported my cadence! argh... Could anybody suggest a better method of translating capture to DEHDL

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Importante Question About Allegro PCB Editor

November 25, 2014, 3:19 am
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There was something, ANYTHING, in the new tecnology of PCBs that are not much WORST than the old Orcad Layout Plus? There are not a single step that are intuitive, there are bilions of things wich you want to do but or they are not possible or they are very dificult? The software engineers that developed the app never tried to use it? 

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Environment variable logic edit

November 26, 2014, 9:22 pm
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Hi ,

How can i enable Environment variable logic edit in pcb editor.

I have used was performance L 16.6 SO28.

Please refer the attached image.

Thanks,

Karthik.

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