Hi, when reviewing schematics(paper copies), I found a net(alias is NET_A) is incorrectly connected with another net(alias is NET_B), this means, NET_A and NET_B are shorted together, which is not intended by the designer.
However, the DRC seems unable to report this kind of situation. I tried to put two different alias on the SAME wire(See picture below), and implement DRC(both Electrical rules and Physical rules), no warnings or errors were reported.
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Is there any way for Cadence to find out this kind of potential error ?
Thank you very much!