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Change component footprint while editing Board

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I doesn't know how to change component footprint without going into capture i.e. replace complete footprint with new.

Ex.  I was using TO220  but need TO92.

Place> Update Symbol   can only be used to update the symbol not for replacement.

Thanks

Vikas Dabas


Simulating the IR2104

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I have a design I would like to simulate with my Lite version of OrCAD. I decided to use OrCad because IR only provides MultiSim and OrCad parts files. Is it possible to do a sim in Lite because I don't have a PSpice menu in schematic page 1 view. I've tried in a number of different software packages to sim my IC but I have not been able to do it yet.

Best Regards!

BOM excel file(.xls) should be linked while generation?

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Hi..

I am having the excel BOM already for our organization format in (.xls).  I want to generate BOM, then generated BOM should be open in our organization format.

Then i had tried option------> Open in Excel, but it creates new excel file and get opening. This option not need.

My problem is, to link the existing excel BOM (.xls) file while generation. It's possible in the Capture 16.6 hot fix 16.6_S039.

Thanks in advance.

Exporting the .brd to .dxf file the drill figure is not get enabled.

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While i am exporting the brd to dxf  file i face some simple problems. When i am trying export the dxf, the drill figures not exported during the conversion.

In case i export means, the solder mask layer only get enabled. The error message is shown below for the problem occurred during the export. 

http://postimg.org/image/4qlh14i5p/ . See the image link for the problem.

So me need the solution, while exporting the drill figures should be get enabled in AUTO CAD.

Text block setup in PCB designer

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Hi all,

Is there any mean to permanently setup the text block values in PCB designer (I have one of the latest version 16.6.S039). I have to do it on each PCB I design under setup/design parameters, 'text' thumb then 'setup text sizes'...

Could it be listed in afile on a server which would be accessed by all the client that starts PCB designer ?

Many thanks and kind regards,

Missing Help documentation? ("Learning PSpice")

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Hi! I'm new to Orcad.

I'm a student and i downloaded the lite version of orcad.

Now, my problem is when going to Help/Learning Pspice, this is the window that pops up:

As you can see, I'm missing the content that's supposed to be in the left pane, as shown in the introduction.

I know i sound really dumb, but what am I missing?

Pour keepout

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I would like to have a 100mil border around my board to keep out copper pours.  It will be mounted in metal rails so I don't want the possibility of a short.

It is a square board that I used a rectangle to define the board outline.  So I used z-copy to offset the border in 100mil.  Now I would use change to change the class to... what?  Would it be BOUNDARY:ALL?

Image in Silkscreen

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Is there a way to add images to the silkscreen?  (e.g. company logo)


Route and Package Keepin Different on Top and Bottom

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I've noticed that the Route Keeping and Package Keepin classes only have "All" subclasses.  How can I specify different Route and Package Keepin areas on the top versus the bottom?

dxf update

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Hello,

I got a dxf file from mechanical design to use it as outline. This is OK so far but now they sended a new version with some additional holes inside.

When I import the new dxf, the old design disappearing.

I tried to import in a "dummy" layer, but the same result.

How can I "update" the outline data from this new dxf?


Thank you in advance.

Can Cadence find out the incorrect-connecting : Two Alias on the same wire

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Hi, when reviewing schematics(paper copies), I found a net(alias is NET_A) is incorrectly connected with another net(alias is NET_B), this means, NET_A and NET_B are shorted together, which is not intended by the designer.

However, the DRC seems unable to report this kind of situation. I tried to put two different alias on the SAME wire(See picture below), and implement DRC(both Electrical rules and Physical rules), no warnings or errors were reported. 

Is there any way for Cadence to find out this kind of potential error ?

Thank you very much!

Can cadence do the Derating checks?

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Hi , I am doing the derating checks for our schematics, manually, one by one, this is laborious...

Generally, derating should be considered during design process when choosing the component, but for some reason, we are required to check all the components' derating status before final release of schematics.

Does Cadence have this kind of function?Could I write some custom scripts to do so?Even if just resistors and capacitors could be automatically checked by software, it will still save us a lot of time...

Thanks!

Constraint Parallel Rules

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Would anyone please able to answer whether or not parallel rules override spacing rules or do spacing rules override parallel rules?

How can i create a netlist from only one of multiple schematic?

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Hi!

I created more schematic in CAPTURE CIS. I want to create individual PCB plan for each one. Can i make an individual netlist from one of them each, or i have to create individual design for them to make it work?

Regards.

Usane.

Silkscreen top text not viewed in GC prevue?

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I had created the artwork generation, Then i had tried to import the artwork on GC prevue tool. When i try to import SST layer, text are not visible,same time i view texts enabled in Allegro PCB editor. 

I didn't mirror SST layer. I had tried to view on the View mate tool also. The same problem occurred ?


Can i change font in the Allegro PCB Editor?

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Hi..

I had tried the settings to change font after installation. In the PCB editor, in the user preference editor, "Kanji" font used. The default of font is used for all versions i think so.

What are settings change font?

I want to change " Kanji" font -----> " Times new Roman /  Arial "  font will possible or not?

Copper Pours

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I am still a noob when it comes to the PCB portion of Orcad.  I have a 4 layer board and am ready to make the pours for the ground/power planes.  How is this done properly?  I have done:

  1. set a "keep in" rectangle inset in from the board outline.
  2. Add: Frectangle on the ground layer
  3. Select the "0" net


However, when I do this, all of my through holes give me a DRC error: Thru Pin to Shape Spacing

I also get an error for the keep in layer: Shape to Route Keepin Spacing

Find trace by width

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I laid a few traces down that are of pretty thin thickness.  Is there a way to "Find" traces by their thickness so I can beef them up?  Or do they need to be done individually?

Using scriptpath

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Hi,

Before updating to 16.6, the "Setup > User Preferences > Paths > Config > scriptpath" seemed to work fine when using "File > Script... > Library... > 'select file' > Replay". Now the file still shows up in the "Library..." list via the "scriptpath" configuration but when "Replay" is clicked the following error occurs:

"E - File does not exist: <filename>"


Why is this? The file is most definitely exists in the "scriptpath".

Thanks,

Aric

Enable of Full screen cursor?

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How to enable the full screen cursor in Allegro PCB editor 16.6?

What is the option to enable /  disable it , whenever i need it ?

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