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Changing silkscreen symbol from solid fill to unfilled

February 5, 2015, 1:32 pm
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I'm using OrCAD PCB Designer Professional 16.5 in Windows 7. I'd really like to know how to change a silkscreened circle from solid fill to unfilled. In other words, just have a hollow circle where I can specify the line width.

Here's the information from Show Element:

 

LISTING: 1 element(s)

             < SHAPE >

       class         PACKAGE GEOMETRY        subclass      SILKSCREEN_TOP

  Shape is solid filled   Area:   0.0491  (sq in)

Exterior boundary:   arc seg:xy (795.00 1785.00) xy (795.00 1785.00) width (0.00)     center-xy:  (670.00 1785.00) radius (125.00)   CW

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Merge Two Board file directly?

February 6, 2015, 1:27 am
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How to merge two different board file directly.????????

Without joining schemetic.

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BOM Report with Alternates in HDL

February 8, 2015, 6:50 pm
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Hi,

Is it possible to generate BOM with different alternates automatically in Design Entry HDL?

Example:

STATUS     VALUE     VENDOR     PART_NUMBER          INTERNAL_PN

Pref             47K          Yageo          RC0603JR-0747KL     123-456

Alt1             47K          KOA              RK73B1JTTX4T3J        123-456

Pref is the component used in the schematic design and Alt1 is the alternate part for the preferred one.  I want to list all possible alternates for the the preferred part placed in the schematic design.  Alternates are identified by the Internal_PN.  All parts with same Internal_PN must be displayed in the bom under the preferred part.

Thanks,

Maberu

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On IPC 2581 data transfer standard problem?

February 9, 2015, 12:54 am
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Hi..

Just  recent days i had start to learn about  "IPC 2581- data transfer standard"  with some tutorial & IPC  website.I had read article by Jerry “GenPart” Grzenia in cadence forum, some doubts are raised during the exporting the file.

 I had tried export of the file in full design mode, in that layer mapping mode and film creation option tab provided. We want to use two tab options while exporting.

Whether i want any configuring of layer mapping edit & film creation  during the exporting the (.XML) file. 

Can anyone help to understand options provided in the IPC 2581 format standard.

Thanks in advance for help. 

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Through hole lead over the opposite side of Package Keep-out.

February 10, 2015, 10:28 pm
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We had issue in latest design. Through hole component plate pad falls over the opposite side of package keep-out. But for this no DRC found in allegro. If anyone help me to solve this issue in Allegro..

Regards,

GKN

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How to display the component's properties in proper position?

February 11, 2015, 12:44 am
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Hi!

When I place components from capture CIS explorer, for example, a capacitor, it displays three properties: value, tolerance, and voltage, as shown in left figrue C1784. I have to manually adjust the position of these properties' texts to achieve a better looking like the right figure C1785.

Is there any method to make some configrations or settings in components lilbrary, so we can directly display properties texts in porper positions when I place the components? This will save us a lot of time.

Thanks a lot!

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Can't load .dxf file in PowerSI

February 11, 2015, 8:15 am
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Hello,

Since some time (when I started it was Ok) loading .dxf file in PowerSI fails and following message appears:

Can not find SpeedEdit, make sure you have installed speed edit properly

Probably I've carelessly changed some setting ... I've searched through PowerSI options, but found nothing relevant.

Thanks in advance

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Change names of Subclasses/Layers?

February 11, 2015, 8:27 am
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Hey guys, I've been looking around for a SKILL command that will allow me to rename a layer in the stackup (like you can visually from the stackup window). What I'm trying to script is the process of inserting a layer between two existing layers in an existing design and updating all the necessary portions of the file, namely that the layer names need to make sense. For instance if I add a new layer between Lay1 and Lay2 in the following stackup:

TOP

Lay1

Lay2

Lay3

BOT

I need it to now be:

TOP

Lay1

Lay2

Lay3

Lay4

BOT

Rather than:

TOP

Lay1

Lay4

Lay2

Lay3

BOT

Does anyone know of a way to get this to work?

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Lower Case Pin numbers

February 12, 2015, 12:09 pm
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I am designing a footprint for D38999 mil-spec connector that has pin numbers uppercase "A" and lower case "a". Does anyone know how to achieve this? The lower case "a" get changed to uppercase.

Thanks

Ben

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automatic refdes change

February 13, 2015, 1:39 am
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There is any option having to change the component refdes name automatically from site to site.

Eg :- if i use the resistor R1_S1 in page 1 means, when i copy this resistor and past in to page 2 it automatically need to change as R1_s2

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concept HDL

February 13, 2015, 1:41 am
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Can anybody know, where i can get CONCEPT HDL complete tutorial

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Cadence TCL: How to get user input

February 13, 2015, 10:25 am
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I would like to ask the user for a text input to use in my tcl script.

I have tried gets stdin, but the command window returns an error: channel "stdin" wasn't opened for reading.  How do I open the stdin channel?

Is it possible to launch a dialog window to prompt the user instead? Something like this:

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Specctra Do Files

February 14, 2015, 11:46 pm
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Hi.  I'm a beginner in Specctra Tool.

How can I get some useful Do files except Cadence reference Do files?

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swaping pin labels in Concept HDL

February 16, 2015, 6:56 am
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Hello,


I am currently using symbols where the pins are swappable but when I swap it in Concept HDL, the pin labels don't swap along with the pin.  For example, if I have a NAND gate that has two inputs, A and B, when I swap the pins, the label should follow with the pin swap.  Is there a way to swap pin labels on the symbol when the pins are swapped in Concept HDL?


thank you


Davang

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Changing 0604 Footprint to 0402

February 16, 2015, 12:41 pm
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I have changed the size of the Padstack and the Package Outline, however I cannot seem to move the Padstack of a simple Capacitor.  I need to move the Padstack associated with Pin 2 of the Cap, but I am stuck.  Any help would be greatly appreciated.

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Command line arguments to start OrCAD Capture with different license options?

February 17, 2015, 8:37 am
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Is there any command line arguments for capture.exe (capture.exe -xxxxx) to start OrCAD Capture with different license options?  Something similar to 'Allegro.exe - orcad' that can start Allegro PCB Editor with OrCAD PCB Designer license (with overrides the default set).

I know I can always use 'File'->'Change Product...' to switch between different licenses but I am just wondering if command line option is available?

Thank  you.

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Via Stitching

February 17, 2015, 9:43 am
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More noob questions.  I have a small 4 layer board and would like to stitch the ground plane with the top and bottom pours with vias on a grid.  This brings up a number of noob questions:


1.  How do you place a via?  I only know how to place a via in the course of routing a trace (right click -> add via).

2.  Is there a way to turn off pours?  I go into the "Visibility" tab and turned off the power and ground planes, but I don't know how to turn off the top and bottom layer ground pours.

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Allegro Sigrity design flow/tool choice

February 17, 2015, 10:52 am
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Hello,

I'm looking for a solution of simulation a structure, consisting of several conductors placed on 2 layers (please see the picture below).

Here are principal simulation tasks:

  • Calculate mutual capacitances between conductors

  • Do transition simulations: apply electrical signal (e.g. square pulse) to one conductor and see responses on other conductors

2nd task probably cannot be realized with one board solution because the structure has no ground. So, the second board with driver that generates square pulse is necessary. But it seems that multiboard design isn't supported (at least in PowerSI and SPEED2000).

 

 

How to proceed.

 

Thanks in advance.

 


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0.8mm BGA routing IPC class 3

February 17, 2015, 11:53 am
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Has anyone here successfully routed a 400+ pin 0.8mm pitch BGA that met IPC class 3 requirements?

If so, how?

Thanks

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Allegro to DXDesigner back annotation

February 17, 2015, 2:25 pm
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Hi all,

I think there are some of us who uses DXDesigner as capture tool and Allegro as PCB tool.

Does anyone know of a good way to back annotate the pin swap done on the FPGA on the board level and apply it to DXDesigner with some type of a list or other method?

Appreciate any help.

Thanks!

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