Hi
Is there a way to get ORCAD (16.6) to report (or DRC) the angle at which traces enter pads ?
( I want to allow 45deg angles in traces, but I want to make where a trace hits a pad it does so at 90degree, not 45degree, to avoid acid traps)
thanks for any help
W
Hi,
I'm trying to place a dimension between two parallel lines, but they sit at an angle. When I use the 'Linear Dimension' tool, it only gives me the X or Y distance only.
How do I get and dimension the distance between the two angled lines?
Thanks!
Hi everyone,
I got the following error ':' not found on line 841 when trying to make a netlist so I look at the netlist log file and see the following error:
Scanning netlist files ...
Loading... D:\AMT_KR\EFI\SCHEMATIC BY ME/pstchip.dat
Loading... D:\AMT_KR\EFI\SCHEMATIC BY ME/pstchip.dat
Loading... D:\AMT_KR\EFI\SCHEMATIC BY ME/pstxprt.dat
#38 WARNING(SPCODD-38): Terminating character ':' not found on line 841.
ERROR(SPCODD-47): Packaging can not complete because the file D:\AMT_KR\EFI\SCHEMATIC/pstxprt.dat could not be
loaded. There might be syntax errors in this file. Ensure that the syntax is correct before proceeding.
ERROR(SPCODD-382): Error at line 841 in file D:\AMT_KR\EFI\SCHEMATIC/pstxprt.dat. Error loading the parts list file
#6 ERROR(ORCAP-36026): Unable to read logical netlist data.
Exiting... "D:\Cadence\SPB_16.5\tools\capture\pstswp.exe" -pst -d "d:\amt_kr\efi\schematic\schematic design.dsn" -n "D:\AMT_KR\EFI\SCHEMATIC" -c "D:\Cadence\SPB_16.5\tools\capture\allegro.cfg" -v 3 -l 31 -s "" -j "PCB Footprint" -hpath "HPathForCollision"
INFO(ORCAP-32005): *** Done ***
I don't understand what was the error and did not get any details about this.
Any help is greatly appreciated
I have a working model in ORCAD Capture, but would like to automate simulations and have the data values exported to a spreadsheet or txt file. Basically, I need an automated process to set a current source value, run a transient analysis, calculate rms values of current & voltage at one node, put that value in a spreadsheet. Then, it needs to change the current source value and do all the steps over again until I have covered all of the DC currents over a define range.
I can make a maco, but I'm not sure that it will export data. Is there a way that I can start a macro, then edit the macro file? I would hope to add script that would handle the data management and replicate the process for the range of DC currents I need to cover.
I have the TCL/Tkt manual, but its tedious and lacks simple examples, at least simple enough for a novice like me to follow.
Any help is greatly appreciated :)
Hi,
I'm trying to delay tune some differential pair lines in allegro, but when I open the Constraint Manager in order to see the propagation time for each pair I don't get any numbers there (nor mm nor ns). What am I missing?
Cheers!
Hello,
I have a master library ptf file which contains a row for each of my 50k+ parts.
We have a situation that just arose where these parts are going to use a different part number. To accommodate this, I have recently begun building a new ptf file which will use the same library models as the master ptf but will use different part numbers. This new file currently contains a whopping 15 parts and will never contain all the parts used in the master ptf.
The problem I am encountering is the Component Browser is listing library cells which are not used in the new part table. For instance the master ptf file contains the library "resistor" and this library contains 242 cells. Of these cells, only 4 are used in the new part table. Now when a user selects the "resistor" they are presented 238 cells which contain no items listed in the part table file.
I have looked through the documentation but I cannot find any solutions to this. I would like the component browser to automatically filter the cells which are listed when a library is selected based on if there are any rows for that cell in the ptf file.
I know I can update the cds.lib file to limit which libraries appear in the component browser but I need to go one level deeper.
Any help would be greatly appreciated. If you need more clarification let me know.
Hi,
I am evaluating OrCAD at the moment and have run into a bit of a problem. How do I go about converting a 2 layer board design to a 4 layer one? I can't seem to be able to add additional conductor layers in the cross section manager.
Thanks!
Is there a way to create square and rectangular pads with rounded corners without having to use a custom shape?
Hi,
Can anyone help me with my problem regarding IBIS Model generation for a dual supply device?
I've encountered 2 types of errors due to the negative supply.
ERROR @line 9: Minimum value exceeds typical value
What I did here was I interchanged the values so as to satisfy the "minimum" and "maximum" portions. But I can't tell if it is the right way to do, because I can't simulate my model because of the 2nd error:
ERROR - Model outputbuffer2: The [Rising Waveform]
with [R_fixture]=50 Ohms and [V_fixture_min]=-9.9V
has MIN column DC endpoints of -9.90V and -9.03v, but
an equivalent load applied to the model's I-V tables yields
different voltages (-9.69V and -9.54V),
a difference of 147.05% and 352.51%, respectively.
Any suggestions for the errors mentioned above?
Thanks! :)
Please guide to solve below problem.
I have done many simulation. this is sudden problem.
Session log description
INFO(ORCAP-2191): Creating PSpice Netlist
INFO(ORNET-1041): Writing PSpice Flat Netlist C:\CADENCE\GIRI PROJECT\METRON\6 Parameter\6 Parameter-PSpiceFiles\SCHEMATIC1\SCHEMATIC1.net
INFO(ORNET-1169): Unable to open the property mapping file: devparam.txt. To resolve this problem, ensure that PSpice.ini exists at the correct location. After that check Library Path in simulation settings contains <installation-path>/tools/pspice/library path and then create the netlist again.
INFO(ORNET-1162): Unable to create design property file.
Is there a reason why , no matter what the slide settings are set to, I cannot slide the 45 degree cline below to the right and onto the pad. It stops moving when the north end of the 45 degree trace hits the smt pad.
When i create a BOM from schematic it has a project name added in the top left.
On mine it refers to an old project. Where does this info get taken from?
I get the following error when trying to unfix any via on a DGND net. W- (SPMHGE-325): No instance of property FIXED found on Via at 590.55,498.82 .
The net is unfixed but all the vias are fixed and cannot be unfixed. Any Idea how to solve the problem ?
I would like to have the entire rats nest on before starting a route but then have the entire rats nest turn off during route except for the current net. Is that possible ?
My requirement is drill hole open.
It is solved by a nice guy but one problem is still remains,
Ploting pdf has etch hatched/ lines filled not solid filled. can you tell me...
I have also tried exporting pdf, it is showing filled shape but the color is gray.
Please suggest something.
Vikas Dabas
Hi,all
I would like to get user's Operating in OrCAD. including capture command or other operating!
Are there any method to do this work?
Thanks a lot !
I have two different grounds on capture, one for the digital part of my board and another for the analogue part. When trying to assign the corresponding ground net I have problems with that .. In the grund net property sheet, under the name column there appears the two named grounds on the drop down menu: AGRD and DGRD. Changing the property to DGRD (the digital ground) can be changed but not saved in the design. It revrts back to the analogue ground .. also when I go to pcb editor there is only one ground net (AGRD). Is this suppose to be like this or am I missing something .. I am tryig to split the one ground plane to digital and analogue .. Can someone lead me to a solution .. Thanks !!!
good day guys,
I have board file in .pcb format in Pads 9.3. i want to do is to convert it to .brd file using Cadence Allegro 16.3. please help me solve my problem.
I have also .dsn file for schematic.
thank you in advance,
Arsenick
good day guys,
please help me how to convert .pcb board file in Pads 9.3 to .brd board file in Cadence Allegro 16.3.
i have also schematic file .dsn
thank you in advance,
Arsenick
I'm have a group of fromtos that I would like to allow to the autorouter to route on certain layers but only in limited amounts. (All other nets will be disallowed from using these layers.) The reference guide seems to state pretty clearly how to do this.
[quote]This rule is provided to limit routing on exposed layers. It works in conjunction with the <restricted_layer_length_factor_descriptor> which marks a layer as restricted.
For example:
rule layer sig1 sig4 (restricted_layer_length_factor 1)
marks layers sig1 and sig4 as restricted, and then
circuit class all_nets (max_restricted_layer_length 50)
limits each net in the class all_nets to a maximum of 50 mils on layers sig1 and sig4[/quote]
However, I'm not getting this to work as intended.
This is the most succesful thing I have tried:
circuit group <groupname> (use_layer 2)
rule layer 2 (restricted_layer_length_factor 1)
circuit group <groupname> (max_restricted_layer_length 25)
It seems to be trying to obey if I do this. There are a few bits of routing that are short (still longer than 25 mils but short) but for a handful of them it seems to "give up" and route hundreds of mils on the restricted layer.
If try it without "circuit group <groupname> (use_layer 2)" then it doesn't use the layer at all.
If I try it without "circuit group <groupname> (max_restricted_layer_length 25)" it runs wild on that layer.
Any ideas?