Hello! Maybe you can help me on how to export the library folder of existing design from pcb tool of Cadence 16.5?
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How to export library from pcb tool in version 16.5 Cadence Allegro
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The realistic 3D view of the components is possible in Editor?
Hi...
Now i am currently using the Allegro PCB Editor 16.6. In that doubt, While rendering the .brd -------> 3D view, place bound top is only get viewed. But i can able to see the realistic image as look in real sample components.
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Void that refused to be deleted
I am trying to delete a set of voids on top/bottom etch in that seems to be a leftover from a deleted island.
Tried Shape-> Manual Void/Cavity -> Delete, without success.
Has anyone here encountered similar problem?
Thanks in advance
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Error -16147 Invalid Parameter on AD8436 Model
Hi there:
I downloaded the .CIR model from Analog devices of the AD8436 from http://www.analog.com/media/en/simulation-models/spice-models/ad8436.cir
**** 05/08/15 21:17:40 ****** PSpice 16.5.0 (April 2011) ****** ID# 0 ********
** Profile: "SCHEMATIC1-Wave" [ C:\USERS\MARIO\DROPBOX\PHD\PSPICE\AD8436 PErformance-PSpiceFiles\SCHEMATIC1\Wave.sim ]
**** CIRCUIT DESCRIPTION
******************************************************************************
** Creating circuit file "Wave.cir"
** WARNING: THIS AUTOMATICALLY GENERATED FILE MAY BE OVERWRITTEN BY SUBSEQUENT SIMULATIONS
*Libraries:
* Profile Libraries :
* Local Libraries :
* From [PSPICE NETLIST] section of C:\Cadence\SPB_16.5\tools\PSpice\PSpice.ini file:
.lib "C:\Cadence\SPB_16.5\Custom_Models\AD8436\AD8436.lib"
.lib "C:\Cadence\SPB_16.5\Custom_Models\THS4011\ths4011.lib"
.lib "C:\Cadence\SPB_16.5\Custom_Models\2N4393\2N4393.lib"
.lib "C:\Cadence\SPB_16.5\Custom_Models\AD8130\AD8130.lib"
.lib "C:\Cadence\SPB_16.5\Custom_Models\AD8476.lib"
.lib "C:\Cadence\SPB_16.5\Custom_Models\ad8421.lib"
.lib "C:\Cadence\SPB_16.5\Custom_Models\ad8066.lib"
.lib "nom.lib"
*Analysis directives:
.TRAN 0 200u 0 20u
.PROBE V(alias(*)) I(alias(*)) W(alias(*)) D(alias(*)) NOISE(alias(*))
.INC "..\SCHEMATIC1.net"
**** INCLUDING SCHEMATIC1.net ****
* source AD8436 PERFORMANCE
.EXTERNAL INPUT AC_IN
.EXTERNAL OUTPUT DC_OUT
X_U1 0 N00208 N00164 N00164 AC_IN 0 0 0 N00359 VEE N00284 N00359 DC_OUT
+ DC_OUT VCC VCC VCC N00493 N00497 0 AD8436
C_C1 N00208 N00164 10u
R_R1 N00284 AC_IN 1k
C_C2 0 N00359 3.3u
C_C3 N00493 VCC 0.1u
C_C4 N00497 VCC 10u
V_V1 VCC 0 5Vdc
V_V2 VEE 0 -5Vdc
V_V3 AC_IN 0
+SIN 0 100mV 50K 0 0 0
**** RESUMING Wave.cir ****
.END
**** EXPANSION OF SUBCIRCUIT X_U1 ****
X_U1.V16 X_U1.567 0 0
X_U1.B2 0 N00359 X_U1.I X_U1.I V16
-------------------------------$
ERROR(ORPSIM-16147): Invalid parameter
X_U1.R4 N00493 X_U1.567 1k
X_U1.R6 N00493 N00497 4k
X_U1.R1 N00284 VEE 100k
X_U1.R2 VCC N00284 100k
X_U1.R7 N00359 0 16k
X_U1.G1 0 X_U1.N013 X_U1.N015 N00164 1
X_U1.R5 X_U1.N013 0 1e6
X_U1.V6 X_U1.N015 AC_IN 0.5m
X_U1.I4 AC_IN 0 25p
X_U1.I3 N00164 0 25p
X_U1.R8 N00164 N00164 10k
X_U1.R16 N00164 0 10k
X_U1.C2 N00164 N00164 10p
X_U1.G2 0 X_U1.N008 X_U1.N011 X_U1.N010 1
X_U1.R10 X_U1.N008 0 1e6
X_U1.C3 X_U1.N013 0 10.1e-8
X_U1.C4 X_U1.N008 0 4.3e-7
X_U1.R11 DC_OUT X_U1.N010 16k
X_U1.I6 N00359 0 1.5n
X_U1.I5 DC_OUT 0 1.5n
X_U1.V9 X_U1.N011 N00359 100u
X_U1.V8 X_U1.VCCX X_U1.N009 1.9
X_U1.B3 VCC VEE X_U1.I X_U1.IF V
-------------------------------$
ERROR(ORPSIM-16147): Invalid parameter
+ IBUFVP -V VEE 4.8 160u 0
X_U1.B4 VCC VEE X_U1.I X_U1.IF V
-------------------------------$
ERROR(ORPSIM-16147): Invalid parameter
+ OBUFVP -V VEE 4.8 40u 0
X_U1.B5 VCC VEE X_U1.I X_U1.IF V
-------------------------------$
ERROR(ORPSIM-16147): Invalid parameter
+ VCC - V VEE 4.8 325u 0
X_U1.E2 X_U1.VCCX 0 VCC 0 1
X_U1.E3 X_U1.VEEX 0 VEE 0 1
X_U1.G3 0 DC_OUT X_U1.N008 0 1
X_U1.R12 DC_OUT 0 1
X_U1.C5 DC_OUT 0 3.6e-7
X_U1.G4 0 N00164 X_U1.N013 0 1
X_U1.R13 N00164 0 1
X_U1.C6 N00164 0 8.3e-8
X_U1.R14 0 0 1e6
X_U1.D1 X_U1.N013 X_U1.N014 X_U1.D
X_U1.D2 X_U1.N012 X_U1.N013 X_U1.D
X_U1.V5 X_U1.VCCX X_U1.N014 .875
X_U1.V3 X_U1.N012 X_U1.VEEX .875
X_U1.R9 N00164 0 10e12
X_U1.R15 AC_IN 0 10e12
X_U1.D3 X_U1.N008 X_U1.N009 X_U1.D
X_U1.D4 X_U1.N007 X_U1.N008 X_U1.D
X_U1.V7 X_U1.N007 X_U1.VEEX 0.88
X_U1.G5 N00284 X_U1.N004 N00284 0 1
X_U1.R17 X_U1.N004 N00284 1e6
X_U1.F1 0 X_U1.N005 X_U1.V12 .500125
X_U1.C8 X_U1.N004 N00284 2.62e-8
X_U1.E4 X_U1.N002 N00284 X_U1.N004 N00284 1
X_U1.V12 0 X_U1.N001 0
X_U1.D5 X_U1.N001 X_U1.N002 X_U1.D
X_U1.D6 X_U1.N002 X_U1.N006 X_U1.D
X_U1.V13 X_U1.N006 0 0
X_U1.F2 0 X_U1.N005 X_U1.V13 .499875
X_U1.V11 X_U1.N005 0 0
X_U1.B1 0 N00497 X_U1.I X_U1.I V11
-------------------------------$
ERROR(ORPSIM-16147): Invalid parameter
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Placing multiple parts at the same time
Is there a way to place multiple parts into a Capture schematic at the same time? Or maybe an entire OLB?
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Dimension to be seen in real time than after selecting two points.
Hi
Allegro shows dimension when we select two points which are known,
what if we need to make a point 1200mil away from a known point. How we mark point at specific distance as the tool cannot have such functionality.
It was present in ORCAD 10.5 Layout.
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Extract and use local library from .dsn and .brd in Orcad Standard 16.6
Hi,
I am new into Orcad, but have quite some PCB projects done with Altium and PADS.
Here is my problem - I have *.dsn file with schematics, and *.brd file with the PCB design, but no libraries at all.
From *.brd file it was not a problem to export a library which give me files *.dra, *.pad, *.psm and *.txt
It was not problem to generate netlist and connect schematics and PCB file in a way that Intertoo communication was working and think that was good.
But then when I want to assembly a library from schematics and PCB files, I was almost totally lost.
For example to view a footprint of component in shematics, I try to point the exported library directory
with adding the directory path into:
C: \ Cadence \ SPB_16.5 \ tools \ capture \ CAPTURE.INI
Dir0 = ... (default)
Dir1 = D: \ PCBlibraryDevelop \ PCB \ Cadence \ RFID \ pcb \ package
or adding it into "Environment Editor" under PCB Editor Utilities.
but not which much success.
Well, if I copy all related to a single component files from exported directories to default
C:\Cadence\SPB_16.6\share\pcb\pcb_lib\symbols
footprint is found, but I want to keep separate library directory for each project.
Hope it not sounds very messy, any advice will be appreciated. Thanks in advance!
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Place component by clicking it on circuit
Place new component by directly clicking on component, or group of components in circuit.
I've seen a video on youtube showing the same.
It automatically come to pointer in allegro.
Please help me with that.
Thanks.
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Model Editor Fixed Values for Sweeps
The background to my question: when you are creating a new model (MOSFET) from a data sheet, Model Editor (ME) has a window with the LEVEL 3 parameters at the bottom, and a window in the top right with several tabs with curves; Transconductance, Transfer Curve, Rds(on), Rev. Drain Current etc.. When producing curves, there are always 1 or 2 of 3 parameters that are swept, while one is held constant. For example, with a transfer curve, VDD is held constant, Vgs is swept, and Id is measured, and Vgs vs. Id is plotted.
My question is this: ME does not allow you to enter a value for the fixed parameter, VDD in my example above. If it does have a field somewhere, I have not been able to find it. The same goes for all the other tabs I mentioned above, there is no where to enter the fixed value. So while trying to match the curves with actual data sheet curves or actual bench-swept curves, how can I do it if I don't know what I am matching to?
See attached pic.
Thanks,
.99
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error while running a simulation in pspice
when i run my simulation i am getting an error as follows could somebody help me pls
ERROR -- Subcircuit Sw_tClose used by X_U1 is undefined
ERROR -- Subcircuit Sw_tOpen used by X_U2 is undefined
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SOLDER-MASK OPENING
As per the IPC-7351B standard we will give Solder mask opening 1:1 , but there will be some special cases like fine pitch BGA or Mask bridge must between pads
where the pad of the type NSMD (SM is bigger than pad) or SMD type (SM is smaller than pad).When we have different type of mask opening requirement in Gerber will
it cause any issue for fabricator ? Will they do component level mask requirement check ? What is the general design consideration we should take care while sending Gerber
(Because I knew that few fabricator usually slightly increase the mask opening of all pads to control the SM registration tolerance.)
Any suggestions on this in generic not specific to particular fab. house ?
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how to move the component in windows location in 16.6 ??
Hi everyone,
i need move the component in windows location.for example if i need to move C1153 component so,i enabled symbol only in Find option and in search option i enter the refdes ,once give the enter, window moved in component location.instead of that, i need bring component in windows location.i did this method in 16.3 but it is not working in 16.6 updated version. is i need to enable any thing in user preference.
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Adding new components to existing design
It is something that lost me a lot of time today, and still unresolved.
Basically, just add few new resistors - copy nearest one and paste as much times as I need.
Make needed connections, and use tools-create netlist - create PCB Editor Netlist and Create or Update PCB editor board (Netrev Enabled),
with other options enabled and open board into OrCAD PCB editor. Use old version of the board and write into new one.
So, netlist creation is OK, but new resistors do not appeared. This time PCB library path is well defined into Capture and PCB, intercommunication is working, few new names for nets are changed too, but no new components. *.DRA file, *.PSM file and *.TXT files are into library for those, checked, too.
Any ideas?
In Layout tab I have ECO enabled, too.
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Displaying the DRC error during slide via into copper shape.
When using the slide command and a DRC error is displayed, 2 triangles point at each other , how do you tell what the DRC is ?
I get this error when moving a stacked via into a copper shape(static solid) of the same net name. This occurs on one board I am working on but not on another. Why would you get an error when sliding a same net via into a copper shape ?
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How to find coordinates of selected item
I can click on a component, or pin, or anything else but how can I find its location ?
The command window shows me the location I clocked to select the pin for example, I want to see the coordinates for the center of the pin, HELP
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How can I purge unused padstacks in board database?
OrCAD Capture 16.6, OrCAD PCB Editor 16.6:
I cannot seem to be able to remove unused padstacks from a board database.
I edited an existing complex board (6 layers, hundreds of parts, vias, text elements, etc) as follows:
1. Opened the board and enabled global visibility.
2. Unplaced all symbols (unfixing when necessary).
3. Removed all etch, shapes, lines, text, vias, groups, dimensions, figures etc (i.e. everything visible, unfixing when necessary).
4. Opened the constraint manager, went to the physical contstraints and removed all vias in the via list except one (note there are no BB vias).r
5. Imported logic from a schematic that had just one component from the original design with an unnamed signal net connected to each pin. The part has just 3 pins with two unique padstacks, one of which is a flash shape.
6. Placed the one part and completed the rats.
7. Checked DRC OK, checked the database OK.
When I export libraries to a directory, I should have just one symbol, three padstacks and a flash symbol. Unfortunately, the library directory contains over 200 files, most of them padstacks. I tried back-annotating, re-generating the netlist and importing again, closing and reopening, etc to no avail.
It seems as if the board database never forgets the old unused padstacks. How can I "purge" the database so that I get only the parts and padstacks that are actually there?
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Foot print re usage is made any problem in the Editor?
Hi..
I had created some IGBT and Power modules components etc. etc..., in the layout version.
In case i am re using the existing library files from Layout -------> PCB Editor means, whether it will loss its accuracy any other problems will be occurred during the conversion or while routing.
Me had tried the simple boards while conversion, but my fear is while conversion of modules any problems will occur????
Any one had done this conversion??
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How to display the Net list errors and warnings one line by one ?
While i am trying to export net list in PCB editor, warnings & errors are get displayed.
I am able to see it like an paragraph of such long. It was too irritating.
Any possible way to display the errors and warnings line by line.
Any solution for this?
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Separate hole to Uvia setting
Is there a way to set a different spacing rule for hole to via and hole to a microvia ?
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How to move pins in symbols on component placement of my board?
Now currently I am placing the components on the board.
In that, while i am trying to move the pin directly in component while placed on PCB.Now I am using OrCAD PCB Editor 16.3.
The pins can be directly moved on my board is possible for my OrCAD 16.3?
Any body faced this problem before? Any solution........
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